DSPIC33FJ06GS101 Datasheet, PDF (253/346 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-6: ADCPC1: A/D CONVERT PAIR CONTROL REGISTER 1
R/W-0
IRQEN3⁽¹⁾
bit 15
R/W-0
PEND3⁽¹⁾
R/W-0
SWTRG3⁽¹⁾
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC3<4:0>⁽¹⁾
R/W-0
IRQEN2⁽²⁾
bit 7
R/W-0
PEND2⁽²⁾
R/W-0
SWTRG2⁽²⁾
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC2<4:0>⁽²⁾
R/W-0
bit 8
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
IRQEN3: Interrupt Request Enable 3 bit⁽¹⁾
1 = Enable IRQ generation when requested conversion of channels AN7 and AN6 is completed
0 = IRQ is not generated
PEND3: Pending Conversion Status 3 bit⁽¹⁾
1 = Conversion of channels AN7 and AN6 is pending. Set when selected trigger is asserted
0 = Conversion is complete
SWTRG3: Software Trigger 3 bit⁽¹⁾
1 = Start conversion of AN7 and AN6 (if selected in TRGSRC bits)⁽³⁾
This bit is automatically cleared by hardware when the PEND3 bit is set.
0 = Conversion is not started
Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and
dsPIC33FJ06GS101 devices only.
2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102,
dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only.
3: If other conversions are in progress, then conversion will be performed when the conversion resources are
available.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 251