DSPIC33FJ06GS101 Datasheet, PDF (202/346 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
PTEN
bit 15
U-0
R/W-0
HS/HC-0
R/W-0
R/W-0
R/W-0
R/W-0
—
PTSIDL
SESTAT
SEIEN
EIPU⁽¹⁾ SYNCPOL⁽¹⁾ SYNCOEN⁽¹⁾
bit 8
R/W-0
U-0
SYNCEN⁽¹⁾
—
bit 7
R/W-0
R/W-0
SYNCSRC<1:0>⁽¹⁾
R/W-0
R/W-0
R/W-0
SEVTPS<3:0>⁽¹⁾
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5-4
bit 3-0
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
EIPU: Enable Immediate Period Updates bit⁽¹⁾
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronization Input/Output Polarity bit⁽¹⁾
1 = SYNCIx and SYNCO polarity is inverted (active-low)
0 = SYNCIx and SYNCO are active-high
SYNCOEN: Primary Time Base Sync Enable bit⁽¹⁾
1 = SYNCO output is enabled
0 = SYNCO output is disabled
SYNCEN: External Time Base Synchronization Enable bit⁽¹⁾
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
Unimplemented: Read as ‘0’
SYNCSRC<1:0>: Synchronous Source Selection bits⁽¹⁾
00 = SYNCI1
01 = SYNCI2
10 = Reserved
11 = Reserved
SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits⁽¹⁾
0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event
0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event
•
•
•
1111 = 1:16 Postscaler generates a Special Event Trigger trigger on every sixteenth compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
DS70318D-page 200
Preliminary
© 2009 Microchip Technology Inc.