PIC12F635 Datasheet, PDF (25/196 Pages) Microchip Technology – 8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY

PIC12F635/PIC16F636/639
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
EEIE
R/W-0
LVDIE
R/W-0
CRIE
R/W-0
C2IE⁽¹⁾
R/W-0
C1IE
R/W-0
OSFIE
U-0
R/W-0
—
TMR1IE
bit 7
bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enables the LVD interrupt
0 = Disables the LVD interrupt
bit 5
CRIE: Cryptographic Interrupt Enable bit
1 = Enables the cryptographic interrupt
0 = Disables the cryptographic interrupt
bit 4
C2IE: Comparator 2 Interrupt Enable bit⁽¹⁾
1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt
bit 3
C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
bit 2
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = Disables the oscillator fail interrupt
bit 1
Unimplemented: Read as ‘0’
bit 0
TMR1IE: Timer1 Interrupt Enable bit
1 = Enables the Timer1 interrupt
0 = Disables the Timer1 interrupt
Note 1: PIC16F636/639 only.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 23