DSPIC30F1010 Datasheet, PDF (24/286 Pages) Microchip Technology – 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers

dsPIC30F1010/202X
2.3 Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
1. DIVF – 16/16 signed fractional divide
2. DIV.sd – 32/16 signed divide
3. DIV.ud – 32/16 unsigned divide
4. DIV.sw – 16/16 signed divide
5. DIV.uw – 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT.
The divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly
and correctly specified in the REPEAT instruction, as
shown in Table 2-1 (REPEAT will execute the target
instruction {operand value + 1} times). The REPEAT
loop count must be set up for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Note:
The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
TABLE 2-1: DIVIDE INSTRUCTIONS
Instruction
Function
DIVF
DIV.sd
DIV.ud
DIV.sw
DIV.uw
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm / Wn → W0; Rem → W1
Unsigned divide: Wm / Wn → W0; Rem → W1
DS70178C-page 22
Preliminary
© 2006 Microchip Technology Inc.