DSPIC30F1010 Datasheet, PDF (126/286 Pages) Microchip Technology – 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers

dsPIC30F1010/202X
12.5 Primary PWM Time Base
There is a Primary Time Base (PTMR) counter for the
entire PWM module, In addition, each PWM generator
has an individual time base counter.
The PTMR determines when the individual time base
counters are to update their duty cycle and phase-shift
registers. The master time base is also responsible for
generating the Special Event Triggers and timer-based
interrupts. Figure 12-12 shows a block diagram of the
primary time base logic.
FIGURE 12-12: PTMR BLOCK DIAGRAM
PERIOD
13
Equality Comparator
>
13
PR_MATCH
Reset
PTMR
Clk
The primary time base may be reset by an external
signal specified via the SYNCSRC<2:0> bits in the
PTCON register. The external reset feature is enabled
via the SYNCEN bit in the PTCON register. The pri-
mary time base reset feature supports synchronization
of the primary time base with another SMPS dsPIC
DSC device or other circuitry in the user’s application.
The primary time base logic also provides an output
signal when a period match occurs that can be used to
synchronize an external device such as another
SMPS dsPIC DSC.
12.5.1 PTMR SYNCHRONIZATION
Because absolute synchronization is not possible, the
user should program the time base period of the sec-
ondary (slave) device to be slightly larger than the pri-
mary device time base to ensure that the two time
bases will reset at the same time.
12.6 Primary PWM Time Base Roll
Counter
The primary time base has an additional 6-bit counter
that counts the period matches of the primary time
base. This ROLL counter enables the PWM genera-
tors to stagger their trigger events in time to the ADC
module. This counter is not accessible for reading.
Each PWM generator has six bits (TRGSTRT<5:0>) in
the TRGCONx registers. These bits are used to spec-
ify the start enable for each TRIGx postscaler con-
trolled by the TRGDIV<2:0> bits in the TRGCONx
registers.
The TRGDIV bits specify how frequently a trigger
pulse is generated, and the ROLL bits specify when
the sequence begins. Once the TRIG postscaler is
enabled, the ROLL bits and the TRGSTRT bits have
no further effect until the PWM module is disabled and
then reenabled.
The purpose of the ROLL counter and the TRGSTRT
bits is to allow the user to spread the system work load
over a series of PWM cycles.
An additional use of the ROLL counter is to allow the
internal FRC oscillator to be varied on a PWM cycle
basis to reduce peak EMI emissions generated by
switching transistors in the power conversion
application.
The ROLL counter is cleared when the PWM module
is disabled (PTEN = 0), and the TRIGx postscalers are
disabled, requiring a new ROLL versus TRGSTRT
match to begin counting again.
12.7 Individual PWM Time Base(s)
Each PWM generator also has its own PWM time
base. Figure 12-13 shows a block diagram for the indi-
vidual time base circuits. With a time base per PWM
generator, the PWM module can generate PWM out-
puts that are phase shifted relative to each other, or
totally independent of each other. The individual PWM
timers (TMRx) provide the time base values that are
compared to the duty cycle registers to create the
PWM signals. The user may initialize these individual
time base counters before or during operation via the
phase-shift registers. The primary (PTMR) and the
individual timers (TMRx) are not user readable.
DS70178C-page 124
Preliminary
© 2006 Microchip Technology Inc.