DSPIC30F6010 Datasheet, PDF (200/218 Pages) Microchip Technology – High-Performance Digital Signal Controllers

dsPIC30F6010
TABLE 24-38: I²C BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Characteristic
Min
Max Units
Conditions
IS10 TLO:SCL Clock Low Time 100 kHz mode
4.7
—
µs
400 kHz mode
1.3
1 MHz mode⁽¹⁾
0.5
IS11 THI:SCL Clock High Time 100 kHz mode
4.0
—
µs
—
µs
—
µs
400 kHz mode
0.6
—
µs
1 MHz mode⁽¹⁾
0.5
—
µs
IS20 TF:SCL SDA and SCL 100 kHz mode
—
300 ns
Fall Time
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode⁽¹⁾
—
100 ns
IS21 TR:SCL SDA and SCL 100 kHz mode
—
1000 ns
Rise Time
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode⁽¹⁾
—
300 ns
IS25 TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
1 MHz mode⁽¹⁾
100
—
ns
—
ns
IS26 THD:DAT Data Input
100 kHz mode
0
—
ns
Hold Time
400 kHz mode
0
0.9 µs
1 MHz mode⁽¹⁾
0
0.3 µs
IS30 TSU:STA Start Condition 100 kHz mode
4.7
Setup Time
400 kHz mode
0.6
1 MHz mode⁽¹⁾
0.25
—
µs
—
µs
—
µs
IS31 THD:STA Start Condition 100 kHz mode
4.0
—
µs
Hold Time
400 kHz mode
0.6
1 MHz mode⁽¹⁾
0.25
—
µs
—
µs
IS33 TSU:STO Stop Condition 100 kHz mode
4.7
—
µs
Setup Time
400 kHz mode
0.6
1 MHz mode⁽¹⁾
0.6
—
µs
—
µs
IS34 THD:STO Stop Condition 100 kHz mode
4000
—
ns
Hold Time
400 kHz mode
600
1 MHz mode⁽¹⁾
250
—
ns
ns
IS40 TAA:SCL Output Valid From 100 kHz mode
0
3500 ns
Clock
400 kHz mode
1 MHz mode⁽¹⁾
0
1000 ns
0
350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode
4.7
—
µs
400 kHz mode
1.3
1 MHz mode⁽¹⁾
0.5
—
µs
—
µs
IS50 CB
Bus Capacitive
—
400 pF
Loading
Note 1: Maximum pin capacitance = 10 pF for all I²C pins (for 1 MHz mode only).
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz.
—
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
—
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
—
—
Only relevant for repeated
Start condition
After this period the first
clock pulse is generated
—
—
—
Time the bus must be free
before a new transmission
can start
—
DS70119D-page 198
Preliminary
 2004 Microchip Technology Inc.