KSZ9031MNX Datasheet, PDF (20/73 Pages) Micrel Semiconductor – The KSZ9031MNX is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physicallayer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable.

KSZ9031MNX
3.10 MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indi-
cation).
• 10 Mbps and 100 Mbps are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
In MII operation, the MII pins function as follows:
• The PHY sources the transmit reference clock, TX_CLK, at 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.
• The PHY recovers and sources the receive reference clock, RX_CLK, at 25 MHz for 100 Mbps and 2.5 MHz for
10 Mbps.
• TX_EN, TXD[3:0], and TX_ER are driven by the MAC and transition synchronously with respect to TX_CLK.
• RX_DV, RXD[3:0], and RX_ER are driven by the KSZ9031MNX and transition synchronously with respect to
RX_CLK.
• CRS and COL are driven by the KSZ9031MNX and do not have to transition synchronously with respect to either
TX_CLK or RX_CLK.
The KSZ9031MNX combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/
1000 Mbps. After power-up or reset, the KSZ9031MNX is configured to GMII/MII mode if the MODE[3:0] strap-in pins
are set to ‘0001’. See the Strapping Options - KSZ9031MNX section.
The KSZ9031MNX has the option to output a 125 MHz reference clock on CLK125_NDO (Pin 55). This clock provides
a lower-cost reference clock alternative for GMII/MII MACs that require a 125 MHz crystal or oscillator. The 125 MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9031MNX provides a dedicated transmit clock output pin (TX_CLK, Pin 57) for MII mode, which is sourced by
the KSZ9031MNX for 10/100 Mbps speed.
3.10.1 MII SIGNAL DEFINITION
Table 3-4 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-4: MII SIGNAL DEFINITION
MII Signal Name
(per spec)
MII Signal Name
(per KSZ9031MNX)
Pin Type (with
respect to PHY)
Pin Type (with
respect to MAC)
Description
TX_CLK
TX_EN
TXD[3:0]
TX_ER
RX_CLK
RX_DV
RXD[3:0]
RX_ER
CRS
COL
TX_CLK
TX_EN
TXD[3:0]
TX_ER
RX_CLK
RX_DV
RXD[3:0]
RX_ER
CRS
COL
Output
Input
Input
Input
Output
Output
Output
Output
Output
Output
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
Transmit Reference Clock
(25 MHz for 100 Mbps, 2.5 MHz for
10 Mbps)
Transmit Enable
Transmit Data[3:0]
Transmit Error
Receive Reference Clock
(25 MHz for 100 Mbps, 2.5 MHz for
10 Mbps)
Receive Data Valid
Receive Data[3:0]
Receive Error
Carrier Sense
Collision Detection
DS00002096C-page 20
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