DSPIC30F2020-30I Datasheet, PDF (188/286 Pages) Microchip Technology – 28/44-Pin High-Performance Switch Mode Power Supply

dsPIC30F1010/202X
16.17 A/D Sample and Convert Timing
The sample and hold circuits assigned to the input pins
have their own timing logic that is triggered when an
external sample and convert request (from PWM or
TMR) is made. The sample and hold circuits have a
fixed two clock data sample period. When the sample
has been acquired, then the ADC control logic is noti-
fied of a pending request, then the conversion is
performed as the conversion resources become
available.
The ADC module always converts pairs of analog input
channels, so a typical conversion process requires 24
clock cycles.
FIGURE 16-3:
DETAILED CONVERSION SEQUENCE TIMINGS, SEQSAMP = 0, NOT BUSY
adc_clk
TAD
sample_even
sample_odd
connect_first
connect_second
convert_en
10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st
capture_first_data
capture_second_data
state counter
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0 1 2
DS70178C-page 186
Preliminary
© 2006 Microchip Technology Inc.