PIC32MX440F512H-80I Datasheet, PDF (171/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
8.3 Single Vector Mode
On any form of Reset, the interrupt controller initializes
to Single Vector mode. When the MVEC (INT-
CON<12>) bit is ‘0’, the interrupt controller operates in
Single Vector mode. In this mode, the CPU always vec-
tors to the same address.
Note:
Users familiar with MIPS32 Architecture
must note that the M4K core in
PIC32MX3XX/4XX is still operating in
External Interrupt Controller (EIC) mode.
The PIC32MX3XX/4XX achieves Single
Vector mode by forcing all IRQs to use a
vector number of 0x00. Because the M4K
core in PIC32MX3XX/4XX always oper-
ates in EIC mode, the single vector behav-
ior through “Interrupt Compatibility Mode,”
as defined by MIPS32 Architecture, is not
recommended.
To configure the CPU in Single Vector mode, the follow-
ing CPU registers (IntCtl, Cause, and Status) and INT-
CON register must be configured as follows:
• EBase ≠ 00000
• VS (IntCtl<9:5>) ≠ 00000
• IV (Cause<23>) = 1
• EXL (Status<1>) = 0
• BEV (Status<22>) = 0
• MVEC (INTCON<12>) = 0
• IE (Status<0>) = 1
EXAMPLE 8-1: SINGLE VECTOR MODE INITIALIZATION
/*
Set the CP0 registers for multi-vector interrupt
Place EBASE at 0xBD000000
This code example uses MPLAB C32 intrinsic functions to access CP0 registers.
Check your compiler documentation to find equivalent functions or use inline assembly
*/
unsigned int temp;
asm volatile(“di”);
// Disable all interrupts
temp = _CP0_GET_STATUS();
temp |= 0x00400000;
_CP0_SET_STATUS(temp);
// Get Status
// Set BEV bit
// Update Status
_CP0_SET_EBASE(0xBD000000);
_CP0_SET_INTCTL(0x00000020);
// Set an EBase value of 0xBD000000
// Set the Vector Spacing to non-zero value
temp = _CP0_GET_CAUSE();
temp |= 0x00800000;
_CP0_SET_CAUSE(temp);
// Get Cause
// Set IV
// Update Cause
temp = _CP0_GET_STATUS();
temp &= 0xFFBFFFFD;
_CP0_SET_STATUS(temp);
// Get Status
// Clear BEV and EXL
// Update Status
INTCONCLR = 0x1000;
// Clear MVEC bit
asm volatile(“ei”);
// Enable all interrupts
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 169