USB3613 Datasheet, PDF (13/57 Pages) SMSC Corporation – USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications

USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
NUM
BALLS
1
1
1
1
1
1
NAME
Reference
Clock Select
1 Input
System Reset
Input
External USB
Transceiver
Bias Resistor
Hub Connect
Input
Charge
Detect 0
Output
Charge
Detect 1
Output
Table 3.1 Ball Descriptions (continued)
SYMBOL
REFSEL1
RESET_N
RBIAS
HUB_CONN
CHRGDET0
CHRGDET1
BUFFER
TYPE
DESCRIPTION
IS
I_RST
AI
This signal, combined with REFSEL0, selects the
reference clock input frequency. The reference
select input must be set to correspond to the
frequency applied to the REFCLK input. Refer to
Section 8.4, "Reference Clock," on page 41 for
additional information.
This active-low signal allows external hardware to
reset the device.
Note:
The active-low pulse must be at least
5us wide. Refer to Section 8.3.2,
"External Chip Reset (RESET_N)," on
page 40 for additional information.
A 12.0kΩ (+/- 1%) resistor is attached from
ground to this pin to set the transceiver’s internal
bias settings.
IS
This signal is used to control the hub
communication stage. The device will transition
to the hub communications stage when this pin is
asserted high. Two methods of use may be used:
Tie to +3.3V: The hub will automatically transition
to the communications stage when configuration
is complete.
Transition from low to high: The hub will
transition to the communications stage after
configuration is complete and this signal
transitions from low to high.
Refer to Section 8.5, "Hub Connect
(HUB_CONN)," on page 42 for additional
information.
O8
This signal, in conjunction with CHRGDET1, can
be configured to communicate information that
can affect the level of current that the system
may draw from the upstream USB VBUS wire.
Refer to Section 8.1.1.1, "Charger Detection
(CHRGDET[1:0])," on page 37 for additional
information.
O8
This signal, in conjunction with CHRGDET0, can
be configured to communicate information that
can affect the level of current that the system
may draw from the upstream USB VBUS wire.
Refer to Section 8.1.1.1, "Charger Detection
(CHRGDET[1:0])," on page 37 for additional
information.
 2014 Microchip Technology Inc.
DS00001714A-page 13