SST25VF080B_15 Datasheet, PDF (13/32 Pages) Microchip Technology – 8 Mbit SPI Serial Flash

SST25VF080B
4.4.8
32-KBYTE AND 64-KBYTE BLOCK-
ERASE
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain
active low for the duration of any command sequence.
The 32-KByte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A₂₃-A₀]. Address bits [A_MS-A₁₅] (A_MS = Most Sig-
nificant Address) are used to determine block address
(BA_X), remaining address bits can be V_IL or V_IH. CE#
must be driven high before the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A₂₃-A₀].
Address bits [A_MS-A₁₅] are used to determine block address
(BA_X), remaining address bits can be V_IL or V_IH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
T_BE for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
FIGURE 4-11:
32-KBYTE BLOCK-ERASE SEQUENCE
CE#
MODE 3
SCK _{MODE 0}
0 1 2345 6 78
15 16
23 24 31
SI
52
ADDR ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
1296 32KBklEr.0
FIGURE 4-12:
64-KBYTE BLOCK-ERASE SEQUENCE
CE#
MODE 3
SCK _{MODE 0}
0 1 2345 6 78
15 16
23 24 31
SI
D8
ADDR ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
1296 63KBlkEr.0
 2015 Microchip Technology Inc.
DS20005045C-page 13