24LC64-I-ST Datasheet, PDF (11/26 Pages) Microchip Technology – 64K I2C™ Serial EEPROM

24AA64/24LC64
FIGURE 6-2:
RANDOM READ
BUS ACTIVITY
S
T
MASTER
A CONTROL
R BYTE
T
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
S
T
A CONTROL
R BYTE
T
S
DATA
T
BYTE
O
P
SDA LINE
S
1
0
1
0
A
2
A
1
A
0
0
XXX
S
1
0
1
0
A
2
A
1
A
0
1
P
A
A
A
A
N
BUS ACTIVITY
C
C
C
C
O
K
K
K
K
A
X = Don’t Care Bit
C
K
FIGURE 6-3:
SEQUENTIAL READ
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
SDA LINE
A
A
A
A
C
C
C
C
BUS ACTIVITY
K
K
K
K
S
DATA n + X
T
O
P
P
N
O
A
C
K
 2003 Microchip Technology Inc.
DS21189H-page 11