PIC16C77X Datasheet, PDF (104/200 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D

PIC16C77X
9.2.2 USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 9-6. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates at
the bit rate or at FOSC.
The USART module has a special provision for multi-
processor communication. When the RX9 bit is set in
the RCSTA register, 9-bits are received and the ninth bit
is placed in the RX9D status bit of the RSTA register.
The port can be programmed such that when the stop
bit is received, the serial port interrupt will only be acti-
vated if the RX9D bit = 1. This feature is enabled by
setting the ADDEN bit RCSTA<3> in the RCSTA regis-
ter. This feature can be used in a multi-processor sys-
tem as follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by the RX9D bit being a ‘1’ (instead of a ‘0’ for
a data byte). If the ADDEN bit is set in the slave’s
RCSTA register, all data bytes will be ignored. How-
ever, if the ninth received bit is equal to a ‘1’, indicating
that the received byte is an address, the slave will be
interrupted and the contents of the RSR register will be
transferred into the receive buffer. This allows the slave
to be interrupted only by addresses, so that the slave
can examine the received byte to see if it is addressed.
The addressed slave will then clear its ADDEN bit and
prepare to receive data bytes from the master.
When ADDEN is set, all data bytes are ignored. Fol-
lowing the STOP bit, the data will not be loaded into the
receive buffer, and no interrupt will occur. If another
byte is shifted into the RSR register, the previous data
byte will be lost.
The ADDEN bit will only take effect when the receiver
is configured in 9-bit mode.
The receiver block diagram is shown in Figure 9-6.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
9.2.3 SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired, set
bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if enable
bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
DS30275A-page 104
Advance Information
© 1999 Microchip Technology Inc.