SST38VF6401B Datasheet, PDF (10/58 Pages) Microchip Technology – 64 Mbit (x16) Advanced Multi-Purpose Flash Plus

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B
Bypass mode can be entered while in Erase-Suspend,
but only Bypass Word-Program is available for those
blocks that are not suspended. Bypass Block-Erase,
Bypass Chip-Erase, Erase-Suspend, and Erase-
Resume are not available. In order to resume an Erase
operation, the Bypass mode must be exited before
issuing Erase-Resume. For more information about
Bypass mode, see “Bypass Mode” on page 13.
4.7 Chip-Erase Operation
The SST38VF6401B/6402B/6403B/6404B devices
provide a Chip-Erase operation, which erases the
entire memory array to the ‘1’ state. This operation is
useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a
six-byte command sequence with Chip-Erase com-
mand (10H) at address 555H in the last byte sequence.
The Erase operation begins with the rising edge of the
sixth WE# or CE#, whichever occurs first. During the
Erase operation, the only valid reads are Toggle Bit,
Data# Polling, or RY/BY#. See Table 5-2 for the com-
mand sequence, Figure 6-9 for timing diagram, and
Figure 6-24 for the flowchart. Any commands issued
during the Chip-Erase operation are ignored. If WP# is
low, or any VPBs or NVPBs are in the protect state, any
attempt to execute a Chip-Erase operation is ignored.
During the command sequence, WP# should be stati-
cally held high or low.
4.8 Write Operation Status Detection
To optimize the system Write cycle time, the
SST38VF6401B/6402B/6403B/6404B provide two soft-
ware means to detect the completion of a Write (Pro-
gram or Erase) cycle The software detection includes
two status bits: Data# Polling (DQ₇) and Toggle Bit
(DQ₆). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal
Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system. Therefore, Data# Polling or
Toggle Bit maybe be read concurrent with the comple-
tion of the write cycle. If this occurs, the system may
possibly get an incorrect result from the status detec-
tion process. For example, valid data may appear to
conflict with either DQ₇ or DQ₆. To prevent false
results, upon detection of failures, the software routine
should loop to read the accessed location an additional
two times. If both reads are valid, then the device has
completed the Write cycle, otherwise the failure is valid.
For the Write-Buffer Programming feature, DQ₁
informs the user if either the Write-to-Buffer or Program
Buffer-to-Flash operation aborts. If either operation
aborts, then DQ₁ = 1. DQ₁ must be cleared to '0' by
issuing the Write-to-Buffer Abort Reset command.
The SST38VF6401B/6402B/6403B/6404B also pro-
vide a RY/BY# signal. This signal indicates the status
of a Program or Erase operation.
If a Program or Erase operation is attempted on a pro-
tected block, the operation will abort. After the device
initiates an abort, the corresponding Write Operation
Status Detection Bits will stay active for approximately
200ns (program or erase) before the device returns to
read mode.
For the status of these bits during a Write operation,
see Table 4-1.
4.8.1 DATA# POLLING (DQ₇)
When the SST38VF6401B/6402B/6403B/6404B are in
an internal Program operation, any attempt to read
DQ₇ will produce the complement of true data. For a
Program Buffer-to-Flash operation, DQ7 is the comple-
ment of the last word loaded in the Write-Buffer using
the Write-to-Buffer command. Once the Program oper-
ation is completed, DQ₇ will produce valid data. Note
that even though DQ₇ may have valid data immediately fol-
lowing the completion of an internal Write operation, the
remaining data outputs may still be invalid. Valid data on the
entire data bus will appear in subsequent successive Read
cycles after an interval of 1 µs.
During an internal Erase operation, any attempt to read
DQ₇ will produce a ‘0’. Once the internal Erase opera-
tion is completed, DQ₇ will produce a ‘1’. The Data#
Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Block- or Chip-
Erase, the Data# Polling is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 6-7 for Data#
Polling timing diagram and Figure 6-21 for a flowchart.
4.8.2
TOGGLE BITS (DQ₆ AND DQ₂)
During the internal Program or Erase operation, any
consecutive attempts to read DQ₆ will produce alternat-
ing ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When
the internal Program or Erase operation is completed,
the DQ₆ bit will stop toggling, and the device is then
ready for the next operation. For Block- or Chip-Erase,
the toggle bit (DQ₆) is valid after the rising edge of sixth
WE# (or CE#) pulse. DQ₆ will be set to ‘1’ if a Read
operation is attempted on an Erase-Suspended Block.
If Program operation is initiated in a block not selected
in Erase-Suspend mode, DQ₆ will toggle.
An additional Toggle Bit is available on DQ₂, which can
be used in conjunction with DQ₆ to check whether a
particular block is being actively erased or erase-sus-
pended. Table 4-1 shows detailed bit status informa-
tion. The Toggle Bit (DQ₂) is valid after the rising edge
of the last WE# (or CE#) pulse of Write operation. See
Figure 6-8 for Toggle Bit timing diagram and Figure 6-
21 for a flowchart.
DS25002B-page 10
Preliminary
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