24FC128 Datasheet, PDF (10/26 Pages) Microchip Technology – 128K I2C CMOS Serial EEPROM

24AA128/24LC128/24FC128
8.0 READ OPERATION
8.2 Random Read
Read operations are initiated in much the same way as
write operations with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX128 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX128 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX128 discontinues transmission (Figure 8-1).
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX128 as part of a write operation (R/W bit set to
‘0’). Once the word address is sent, the master gener-
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal address pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX128 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition, which
causes the 24XX128 to discontinue transmission
(Figure 8-2). After a random Read command, the
internal address counter will point to the address
location following the one that was just read.
8.3 Sequential Read
FIGURE 8-1:
CURRENT ADDRESS
READ
S
BUS ACTIVITY
T
A
MASTER
R
T
Control
Byte
SDA LINE
S
1
0
1
0
AAA
210
1
A
BUS ACTIVITY
C
K
S
Data
T
Byte
O
P
P
N
O
A
C
K
Sequential reads are initiated in the same way as a
random read except that after the 24XX128 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX128 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge
but will generate a Stop condition. To provide
sequential reads, the 24XX128 contains an internal
address pointer which is incremented by one at the
completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 3FFF to address
0000 if the master acknowledges the byte received
from the array address 3FFF.
FIGURE 8-2:
RANDOM READ
BUS ACTIVITY
S
T
MASTER
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
S
T
A
Control
R
Byte
T
Data
S
T
Byte
O
P
SDA LINE
S
1
0
1
0
A
2
A
1
A
0
0
XX
S
1
0
1
0
A
2
A
1
A
0
1
P
A
A
A
A
N
BUS ACTIVITY
C
C
C
C
O
K
K
K
K
A
X = don’t care bit
C
K
FIGURE 8-3:
BUS ACTIVITY
MASTER
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
SDA LINE
A
A
C
C
BUS ACTIVITY
K
K
A
A
C
C
K
K
S
Data (n + X)
T
O
P
P
N
O
A
C
K
DS21191M-page 10
 2004 Microchip Technology Inc.