24C32_04 Datasheet, PDF (10/14 Pages) Microchip Technology – 32K 5.0V I2C Smart Serial EEPROM

24C32
FIGURE 8-1: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
1 _{Write command initiated at byte 0 of page 3 in the array;}
First data byte is loaded into the cache byte 0.
2 64 bytes of data are loaded into cache.
cache page 0
cache cache
cache cache page 1 cache page 2
byte 0 byte 1 ^{• • •} byte 7 bytes 8-15 bytes 16-23
•••
cache page 7
bytes 56-63
3 Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
4 Remaining pages in cache are written
to sequential pages in array.
page 0 page 1 page 2 byte 0 byte 1 • • • byte 7 page 4 • • • page 7 array row n
page 0 page 1 page 2
page 3
page 4 • • • page 7 array row n + 1
5 Last page in cache written to page 2 in next row.
FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
Last 2 bytes
loaded into
page 0 of cache.
3
cache
byte 0
1 Write command initiated; 64 bytes of data
2 Last 2 bytes loaded 'roll over'
loaded into cache starting at byte 2 of page 0.
to beginning.
cache cache
byte 1 byte 2
•••
cache
byte 7
cache page 1 cache page 2
bytes 8-15 bytes 16-23
•••
cache page 7
bytes 56-63
4 Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
5 Remaining bytes in cache are
Write cycle is executed after every page is written. written sequentially to array.
page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4
page 0 page 1 page 2
page 3
6 Last 3 pages in cache written to next row in array.
•••
byte 7 page 4
page 4
•••
•••
page 7
array
row n
page 7
array
row
n+1
DS21061H-page 10
 2004 Microchip Technology Inc.