KSZ8842-MQL Datasheet, PDF (91/141 Pages) Micrel Semiconductor – 2-Port Ethernet Switch with Non-PCI Interface

Micrel, Inc.
Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR
This register contains the PHY ID (low) for the switch port 1 function.
Bit
15-0
Default
0x1430
R/W Description
RO PHYID Low
Low order PHYID bits.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR
This register contains the PHY ID (high) for the switch port 1 function.
Bit
15-0
Default
0x0022
R/W Description
RO PHYID High
High order PHYID bits.
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR
This register contains the auto-negotiation advertisement for the switch port 1 function.
Bit
Default
15
0
14
0
13
0
12-11 0x0
10
1
9
0
8
1
7
1
6
1
5
1
4-0
0x01
R/W Description
Bit is same as:
RO Next page
Not supported.
RO Reserved
RO Remote fault
Not supported.
RO Reserved
RW Pause (flow control capability)
Bank 49 0x02 bit 4
1 = advertise pause ability.
0 = do not advertise pause capability.
RW Reserved
RW Adv 100 Full
Bank49 0x02 bit 3
1 = advertise 100 full-duplex capable.
0 = do not advertise 100 full-duplex capability.
RW Adv 100 Half
Bank49 0x02 bit 2
1= advertise 100 half-duplex capable.
0 = do not advertise 100 half-duplex capability.
RW Adv 10 Full
Bank49 0x02 bit 1
1 = advertise 10 full-duplex capable.
0 = do not advertise 10 full-duplex capability.
RW Adv 10 Half
Bank49 0x02 bit 0
1 = advertise 10 half-duplex capable.
0 = do not advertise 10 half-duplex capability.
RO Selector Field
802.3
October 2007
91
M9999-102207-1.9