KSZ8893MBL Datasheet, PDF (90/116 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8893MQL/MBL
Registers 118 to 120
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can
be used to pass user defined control and status information between the KSZ8893MQL/MBL and the external
processor.
Register 118 (0x76): User Defined Register 1
Bit
Name
R/W Description
7-0
UDR1
R/W
Default
0x00
Register 119 (0x77): User Defined Register 2
Bit
Name
R/W Description
7-0
UDR2
R/W
Default
0x00
Register 120 (0x78): User Defined Register 3
Bit
Name
R/W Description
7-0
UDR3
R/W
Default
0x00
Registers 121 to 131
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC
address table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Bit
Name
R/W Description
7-5
Reserved
R/W Reserved
Do not change the default values.
4
Read High /
R/W = 1, read cycle
Write Low
= 0, write cycle
3-2
Table Select
R/W ^{00 = static MAC address table selected}
01 = VLAN table selected
10 = dynamic MAC address table selected
11 = MIB counter selected
1-0
Indirect
R/W Bits [9:8] of indirect address
Address High
Default
000
0
00
00
Register 122 (0x7A): Indirect Access Control 1
Bit
Name
R/W Description
Default
7-0
Indirect
R/W Bits [7:0] of indirect address
Address Low
0000_0000
Note: A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.
Register 123 (0x7B): Indirect Data Register 8
Bit
Name
R/W Description
Default
7
CPU Read
RO This bit is applicable only for dynamic MAC
Status
address table and MIB counter reads.
= 1, read is still in progress
= 0, read has completed
6-3
Reserved
RO Reserved
0
0000
2-0
Indirect Data RO Bits [66:64] of indirect data
000
[66:64]
February 2010
90
M9999-021110-1.6