MIC7401 Datasheet, PDF (9/68 Pages) Micrel Semiconductor – Configurable PMIC, Five-Channel Buck Regulator plus One-Boost with HyperLight Load®, I2C Control, and Enable

Micrel, Inc.
MIC7401
Pin Description (Continued)
Pin Number
24
25
26
27
28
29
30
31
32
33
34
35
36
EP
Pin Name
PVIN6O
PVIN6
PVIN1
SW1
PGND1
OUT1
EN
AVIN
AGND
NC
NC
PG
PGND2
ePad
Description
Power Supply Voltage 6 (Output): This pin is the output of the power disconnect switch for the boost
regulator. When the boost regulator is on, an internal switch provides a current path for the boost
inductor. In shutdown, an internal P-channel MOSFET is turned off and disconnects the boost output
from the input supply. This feature eliminates current draw from the input supply during shutdown. An
input capacitor between PVIN6O and the power ground PGND6 pin is required and place as close as
possible to the IC.
Power Supply Voltage 6 (Input): Input supply to the internal disconnect switch.
Power Supply Voltage 1 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN1 and the power ground PGND1 pin is required and to be
placed as close as possible to the IC.
Switch Pin 1 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor between the output capacitor and the SW1 pin.
Power Ground 1: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative terminals of output capacitors.
Output Voltage Sense 1(Input): This pin is used to sense the output voltage remotely. Connect OUT1
as close to output capacitor as possible to sense output voltage. This feature also provides the path to
discharge the output through an internal 90Ω resistor when disabled. The pull-down feature is
programmed through the PULLD[x] register.
Enable (input): A logic level control of both outputs. The EN pin is CMOS-compatible. Logic
high = enable, logic low = shutdown. In the off state, supply current of the device is greatly
reduced (typically 1µA). When the EN pin goes high, the start-up sequence is initiated.
When EN goes low, all outputs are immediately turned off and the boost output (V_OUT6) is
completely disconnected from the input voltage. The EN pin must be high for the I2C to
communicate with the IC; otherwise, the IC cannot be programmed. Do not let this pin float.
Connect to ground or V_IN. A pull-up resistor of 500kΩ can also be used
Analog Voltage Supply (Input): The start-up sequence begins as soon as the AVIN pin voltage rises
above the IC’s UVLO upper threshold. The outputs do not turn off until AVIN pin voltage falls below
the lower threshold limit. A 2.2µF ceramic capacitor from the AVIN pin to AGND pin must be placed
next to the IC.
Analog Ground: Internal signal ground for all low power circuits. Connect directly to the layer 2 ground
plane. Layer 2 is the point where all the PGNDs and AGND are connected. Do not connect PGND
and AGND together on the top layer.
No Connect. Must be left floating.
No Connect. Must be left floating.
Global Power Good (Output): This is an open drain output that is pulled high when all the regulator
power good flags are high. If an output falls below the power good threshold or a thermal fault occurs,
the global power good flag is pulled low. There is a falling edge de-glitch time of 50µs to prevent false
triggering on output voltage transients. A power good mask feature programmed through the
PGOOD_MASK[x] registers can be used to ignore a power good fault. When masked an individual
power good fault will not cause the global power good output to de-assert. Do not connect the power
good pull-up resistor to a voltage higher than AVIN.
Power Ground 2: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative terminals of output capacitors.
Exposed Pad: Must be connected to the GND plane for full output power to be realized.
March 16, 2015
9
Revision 1.0