MIC7401 Datasheet, PDF (39/68 Pages) Micrel Semiconductor – Configurable PMIC, Five-Channel Buck Regulator plus One-Boost with HyperLight Load®, I2C Control, and Enable

Micrel, Inc.
PCB Layout Guidelines
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
PCB Layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power, signal
and return paths.
The following guidelines should be followed to insure
proper operation:
General
• Most of the heat removed from the IC is due to the
exposed pad (EP) on the bottom of the IC conducting
heat into the internal ground planes and the ground
plane on the bottom side of the board. Use at least 16
vias for the EP to ground plane connection.
• Do not connect the PGND and AGND traces together
on the top layer. The single point connection is made
on the layer 2 ground plane.
• Do not put a via directly in front of a high current pin,
SW, PGND, or PVIN. This will increase the trace
resistance and parasitic inductance.
• Do not place a via in between the input and output
capacitor ground connection. Put it to the inside of the
output capacitor and in the way of the high di/dt
current path.
• Route all power traces on the top layer, as shown in
the example layout.
• Place the input capacitors first and put them as close
as possible to the IC.
IC
• The 2.2µF ceramic capacitor, which is connected to the
AVIN pin, must be located right at the IC. The AVIN pin
is very noise sensitive and placement of the capacitor
is very critical. Use wide traces to connect to the AVIN
and AGND pins.
• The analog ground pin (AGND) must be connected
directly to the ground planes. Do not route the SGND
pin to the PGND Pad on the top layer.
• Use fat traces to route the input and output power
lines.
• Use Layer 5 as an input voltage power plane.
• Layer 2 and the bottom layer (Layer 6) are ground
planes.
MIC7401
Input Capacitor
• A 10µF X5R or X7R dielectrics ceramic capacitor is
recommended on each of the PVIN pins for bypassing.
• Place the input capacitors on the same side of the
board and as close to the IC as possible.
• Keep both the PVIN pin and PGND connections short.
• If possible, place vias to the ground plane close to the
each input capacitor ground terminal, but not in the
way of the high di/dit current path.
• Use either X7R or X5R dielectric input capacitors. Do
not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
• In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the over-voltage
spike seen on the input supply when power is suddenly
applied.
Inductor
• Keep the inductor connection to the switch node (SW)
short.
• Do not route any digital lines underneath or close to
the inductor.
• To minimize noise, place a ground plane underneath
the inductor.
Output Capacitor
• Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground terminal.
In the example layout, all input and output capacitor
ground connections are place back-to-back.
• The OUT[1-6] trace should be separate from the power
trace and connected as close as possible to the output
capacitor. Sensing a long high-current load trace can
degrade the DC load regulation.
March 16, 2015
39
Revision 1.0