MIC5164 Datasheet, PDF (9/23 Pages) Micrel Semiconductor – Dual Regulator Controller for DDR3 GDDR3/4/5 Memory and High-Speed Bus Termination

Micrel, Inc.
Application Information
High-performance memory requires high-speed
signaling. This requires special attention to maintain
signal integrity. Bus termination provides a means to
increase signaling speed while maintaining good signal
integrity. An example of bus termination is the Series
Stub Termination Logic or SSTL. Figure 2 is an example
of an SSTL 2 single-ended series parallel terminated
output. SSTL 2 is a JEDEC signaling standard operating
off a 2.5V supply. It consists of a series resistor (R_S) and
a terminating resistor (R_T). Values of R_S range between
10Ω to 30Ω with a typical of 22Ω, while R_T ranges from
22Ω to 28Ω with a typical value of 25Ω. V_REF must
maintain 1/2 VDD with a ±1% tolerance, while V_TT will
dynamically sink and source current to maintain a
termination voltage of ±40mV from the V_REF line under all
conditions. This method of bus termination reduces
common mode noise, settling time, voltage swings,
EMI/RFI and improves slew rates.
The MIC5165 provides two drive signals, the high-side
MOSFET acts as a pass element to provide output
voltage and low side MOSFET acts as pull-down to
regulate the output termination voltage (V_TT). An internal
error amplifier compares the termination voltage (V_TT)
and V_REF, controlling two external N-Channel MOSFETs
to sink and source current to maintain a termination
voltage (V_TT) equal to V_REF. The N-Channels receive
their enhancement voltage from a separate VCC pin on
the device.
Although the general discussion is focused on SSTL, the
MIC5164 is also capable of providing bus terminations
for SCSI, GTL, HSTL, LV-TTL, Rambus, LV-PECL,
DDR, DDR2, DDR3 memory termination and other
systems.
MIC5164
VDDQ
The VDDQ pin on the MIC5164 provides the source
current through the high-side N-Channel and the
reference voltage to the device. The MIC5164 can
operate at V_DDQ voltages as low as 1.35V. Due to the
possibility of large transient currents being sourced from
this line, significant bypass capacitance will aid in
performance by improving the source impedance at
higher frequencies. Since the reference is simply V_DDQ/2,
perturbations on V_DDQ will also appear at half the
amplitude on the reference. For this reason, low-ESR
capacitors such as ceramics or OS-CON are
recommended on V_DDQ.
V_TT
V_TT is the actual termination point. V_TT is regulated to
V_REF. Due to high speed signaling, the load current seen
by V_TT is constantly changing. To maintain adequate
large signal transient response, large OS-CON and
ceramics are recommended on V_TT. The proper
combination and placement of the OS-CON and ceramic
capacitors is important to reduce both ESR and ESL
such that high-current and high-speed transients do not
exceed the dynamic voltage tolerance requirement of
V_TT. The larger OS-CON capacitors provide bulk charge
storage while the smaller ceramic capacitors provide
current during the fast edges of the bus transition. Using
several smaller ceramic capacitors distributed near the
termination resistors is typically important to reduce the
effects of PCB trace inductance.
VREF
A minimum capacitor value of 120pF from VREF to
ground is required to remove high-frequency signals
reflected from the source (Refer to Figure 4). Large
capacitance values (>1500pF) should be avoided.
Values greater than 1500pF slow down V_REF and detract
from the reference voltage’s ability to track V_DDQ during
high-speed load transients.
Figure 2. SSTL-2 Termination
June 2010
Figure 3. MIC5164 as a DDR Memory Termination
for 3.5A Application
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M9999-061510