MIC5162_10 Datasheet, PDF (9/24 Pages) Micrel Semiconductor – Dual Regulator Controller for DDR3 GDDR3/4/5 Memory and High-Speed Bus Termination

Micrel, Inc.
where I_SINK is the average sink current.
In a typical 3A peak SSTL_2 circuit, power
considerations for MOSFET selection would occur as
follows.
P_D = (V_DDQ −V_TT) × I_SOURCE
P_D = (2.5V −1.25V) × 1.6A
P_D = 2W
This typical SSTL_2 application would require both high-
side and low-side N-Channel MOSFETs to be able to
handle 2 Watts each. In applications where there is
excessive power dissipation, multiple N-Channel
MOSFETs may be placed in parallel. These MOSFETs
will share current, distributing power dissipation across
each device.
The maximum MOSFET die (junction) temperature limits
maximum power dissipation. The ability of the device to
dissipate heat away from the junction is specified by the
junction-to-ambient (θ_JA) thermal resistance. This is the
sum of junction-to-case (θ_JC) thermal resistance, case-
to-sink (θ_CS) thermal resistance and sink-to-ambient
(θ_SA) thermal resistance;
θ_JA = θ_JC + θ_CS + θ_SA
In the example of a 3A peak SSTL_2 termination circuit,
a D-pack N-Channel MOSFET that has a maximum
junction temperature of 125°C has been selected. The
device has a junction-to-case thermal resistance of
1.5°C/Watt. The application has a maximum ambient
temperature of 60°C. The required junction-to-ambient
thermal resistance can be calculated as follows:
θ _JA
=
T_J − T_A
P_D
Where T_J is the maximum junction temperature, T_A is the
maximum ambient temperature and P_D is the power
dissipation.
In this example:
θ _JA
=
T_J − T_A
P_D
125°C - 60°C
θ_JA =
2W
MIC5162
θ_JA = 32.5°C / W
This shows that our total thermal resistance must be
better than 32.5°C/W. Since the total thermal resistance
is a combination of all the individual thermal resistances,
the amount of heat sink required can be calculated as
follows:
θ_SA = θ_JA − (θ_JC + θ_CS)
In this example:
θ_SA = 32.5°C / W - (1.5°C / W + 0.5°C)
θ _SA = 30 .5 °C / W
In most cases, case-to-sink thermal resistance can be
assumed to be about 0.5°C/W.
The SSTL termination circuit for this example, using 2 D-
pack N-Channel MOSFETs (one high side and one on
the low side) will require at least a 30.5°C/W heat sink
per MOSFET. This may be accomplished with an
external heat sink or even just the copper area that the
MOSFET is soldered to. In some cases, airflow may also
be required to reduce thermal resistance.
MOSFET Gate Threshold
N-Channel MOSFETs require an enhancement voltage
greater than its source voltage. Typical N-Channel
MOSFETs have a gate-source threshold (V_GS) of 1.8V
and higher. Since the source of the high side N-Channel
is connected to V_TT, the MIC5162 V_CC pin requires a
voltage greater than the V_GS voltage. For example, the
SSTL_2 termination circuit has a V_TT voltage of 1.25V.
For an N-Channel that has a V_GS rating of 2.5V, the V_CC
voltage can be as low as 3.75V, but not less than 3.0V.
With an N-Channel that has a 4.5V V_GS, the minimum
V_CC required is 5.75V. Although these N-Channels are
driven below their full enhancement threshold, it is
recommended that the V_CC voltage has enough margin
to be able to fully enhance the MOSFETs for large signal
transient response. In addition, low gate thresholds
MOSFETs are recommended to reduce the V_CC
requirements.
March 2010
9
M9999-033110