MIC5162_10 Datasheet, PDF (7/24 Pages) Micrel Semiconductor – Dual Regulator Controller for DDR3 GDDR3/4/5 Memory and High-Speed Bus Termination

Micrel, Inc.
Application Information
High performance memory requires high speed
signaling. This means special attention must be paid to
maintain signal integrity. Bus termination provides a
means to increase signaling speed while maintaining
good signal integrity. An example of bus termination is
the Series Stub Termination Logic or SSTL. Figure 1 is
an example of an SSTL 2 single ended series parallel
terminated output. SSTL 2 is a JEDEC signaling
standard operating off a 2.5V supply. It consists of a
series resistor (R_S) and a terminating resistor (R_T).
Values of R_S range between 10Ω to 30Ω with a typical of
22Ω, while R_T ranges from 22Ω to 28Ω with a typical
value of 25Ω. V_REF must maintain 1/2 VDD with a ±1%
tolerance, while V_TT will dynamically sink and source
current to maintain a termination voltage of ±40mV from
the V_REF line under all conditions. This method of bus
termination reduces common mode noise, settling time,
voltage swings, EMI/RFI and improves slew rates.
The MIC5162 is a high performance linear controller,
utilizing scalable N-Channel MOSFETs to provide
JEDEC-compliant bus termination. Termination is
achieved by dividing down the V_DDQ voltage by half,
providing the reference (V_REF) voltage. An internal error
amplifier compares the termination voltage (V_TT) and
V_REF, controlling 2 external N-Channel MOSFETs to sink
and source current to maintain a termination voltage
(V_TT) equal to V_REF. The N-Channels receive their
enhancement voltage from a separate V_CC pin on the
device.
Although this document focuses mostly on SSTL, the
MIC5162 is also capable of providing bus terminations
for SCSI, GTL, HSTL, LV-TTL, Rambus, LV-PECL,
DDR, DDR2, DDR3 memory termination and other
systems.
MIC5162
V_DDQ
The V_DDQ pin on the MIC5162 provides the source
current through the high-side N-Channel and the
reference voltage to the device. The MIC5162 can
operate at V_DDQ voltages as low as 1.35V. Due to the
possibility of large transient currents being sourced from
this line, significant bypass capacitance will aid in
performance by improving the source impedance at
higher frequencies. Since the reference is simply V_DDQ/2,
perturbations on the V_DDQ will also appear at half the
amplitude on the reference. For this reason, low ESR
capacitors such as ceramics or OS-CON are
recommended on V_DDQ.
V_TT
V_TT is the actual termination point. V_TT is regulated to
V_REF. Due to high speed signaling, the load current seen
by V_TT is constantly changing. To maintain adequate
large signal transient response, large OS-CON and
ceramics are recommended on V_TT. The proper
combination and placement of the OS-CON and ceramic
capacitors is important to reduce both ESR and ESL
such that high-current and high-speed transients do not
exceed the dynamic voltage tolerance requirement of
V_TT. The larger OS-CON capacitors provide bulk charge
storage while the smaller ceramic capacitors provide
current during the fast edges of the bus transition. Using
several smaller ceramic capacitors distributed near the
termination resistors is typically important to reduce the
effects of PCB trace inductance.
V_REF
Two resistors dividing down the V_DDQ voltage provide
V_REF (Figure 3). The resistors are valued at around
17kΩ. A minimum capacitor value of 120pF from V_REF to
ground is required to remove high frequency signals
reflected from the source. Large capacitance values
(>1500pF) should be avoided. Values greater than
1500pF slow down V_REF and detract from the reference
voltage’s ability to track V_DDQ during high speed load
transients.
Figure 1. SSTL-2 Termination
March 2010
Figure 2. MIC5162 as a DDR Memory Termination
for 3.5A Application
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M9999-033110