MIC23060 Datasheet, PDF (9/15 Pages) Micrel Semiconductor – Sequenced Power Management IC with HyperLight Load™ DC/DC and Dual Input LDO™

Micrel, Inc.
Functional Description
DVIN
The main input supply (DVIN) provides power to the
internal MOSFETs for the switch mode regulator. The
DVIN operating range is 2.7V to 5.5V, so an input
capacitor, with a minimum voltage rating of 6.3V is
recommended. Due to the high switching speed, a
minimum 2.2μF bypass capacitor placed close to DVIN
and the power ground (PGND) pin is required. For best
performance a 4.7μF capacitor is recommended, refer to
the layout recommendations for details.
AVIN
The Analog input supply (AVIN) provides power to the
low power, biasing and control circuitry. Due to the high
switching speed of the DC/DC converter, this should
ideally be connected away from the DVIN bypass
capacitor at the input supply. Refer to layout
recommendations for more details.
S1/S2/S3
A logic high signal on the Set pins activates the output
voltage of the devices in various sequencing modes. A
logic low signal on the Set pins deactivates the outputs
in various sequences and reduces supply current to
0.01μA. Full details of start-up/shutdown sequencing are
given in the Application Information section. The
MIC23060 features built-in soft-start circuitry that
reduces in-rush current and prevents the output voltage
from overshooting at start up. Do not leave these pins
floating.
SW
The switch (SW) pin connects directly to one end of the
inductor and provides the current path during switching
cycles. The other end of the inductor is connected to the
load, SNS pin and output capacitor. Due to the high
speed switching on this pin, the switch node should be
routed away from sensitive nodes whenever possible.
MIC23060
SNS
The feedback (SNS) pin is connected to the output of the
DC/DC converter to provide feedback to the control
circuitry. The SNS connection should be placed close to
the output capacitor. Refer to the layout
recommendations for more details.
LDO
The LDO Output (LDO) pin is the output of the Dual
Input LDO™. Power is provided by the DC/DC output
during normal operation and briefly by V_AVIN during some
start-up and Shutdown sequences. A ceramic bypass
capacitor of at least 1μF is required.
DLY
The delay (DLY) pin is connected to an external
capacitor and AGND to set the delay time between the
first regulator output reaching 90% of its regulated
voltage and enabling the second regulator. The same
delay time is also used during shutdown.
AGND
The analog ground (AGND) is the ground path for the
biasing and control circuitry. The current loop for the
signal ground should be separate from the power ground
(PGND) loop. Refer to the layout recommendations for
more details.
PGND
The power ground pin is the ground path for the high
current in PWM mode. The current loop for the power
ground should be as small as possible and separate
from the analog ground (AGND) loop as applicable.
Refer to the layout recommendations for more details.
April 2010
9
M9999-042210-B