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MIC23060 Datasheet, PDF (11/15 Pages) Micrel Semiconductor – Sequenced Power Management IC with HyperLight Load™ DC/DC and Dual Input LDO™
Micrel, Inc.
modes, S2 controls the LDO sequence and S1 controls
the DC/DC sequence. Here is a Truth Table followed by
a flow chart of the sequencing events:
S3
S2
S1 Sequence
X
0
0
ALL OFF
0
0
EN
DC-DC ON 1st / OFF 1st
0
EN
0
LDO ON 1st / OFF 1st
1
0
EN
DC-DC ON 1st / OFF 2nd
1
EN
0
LDO ON 1st / OFF 2nd
X
1
1
ALL ON
MIC23060
For example, an application where the LDO should be
enabled 50ms before the DC/DC and disabled 50ms
after the DC-DC, the pins should be set as follows:
S1 = 0
S3 = 1
CDLY = 50nF
S2 = Enable stimulus
Flow Chart of the Enable & Disable sequence
DLY
The value of capacitor on this pin is used to program the
enable and disable delay times. The delay time follows
the following equation:
TDLY = VDLY.CDLY / IDLY
Where nominally: VDLY = 1.25V, IDLY = 1.25μA
∴ TDLY (ms) = CDLY (nF)
Detail of the delay timer circuit.
Duty Cycle
The typical maximum duty cycle of the MIC23060 is
80%.
Efficiency Considerations
Efficiency is defined as the amount of useful output
power, divided by the amount of power supplied.
Efficiency(%)
=
⎜⎜⎝⎛
VOUT
VIN
× IOUT
× IIN
⎟⎟⎠⎞
× 100
Maintaining high efficiency serves two purposes. It
reduces power dissipation in the power supply,
simplifying thermal design considerations, and it reduces
current consumption for battery powered applications.
Reduced current draw from a battery increases the
devices operating time and is critical in hand held
devices.
There are two types of losses in switching converters;
DC losses and switching losses. DC losses are simply
the power dissipation of I2R. Power is dissipated in the
high side switch during the on cycle. Power loss is equal
to the high side MOSFET RDSON multiplied by the Switch
Current squared. During the off cycle, the low side N-
channel MOSFET conducts, also dissipating power.
Device operating current also reduces efficiency. The
product of the quiescent (operating) current and the
supply voltage represents another DC loss. The current
required driving the gates on and off at a constant 4MHz
frequency and the switching transitions make up the
switching losses.
April 2010
11
M9999-042210-B