MIC22950 Datasheet, PDF (9/22 Pages) Micrel Semiconductor – 10A Integrated Switch Synchronous Buck Regulator with Frequency Programmable to 2MHz

Micrel, Inc.
Functional Description
PVIN, SVIN
PVIN is the input supply to the internal 11mΩ P-Channel
Power MOSFET. This should be connected externally to
the SVIN pin. The supply voltage range is from 2.6V to
5.5V. A 22µF ceramic is recommended for bypassing
each PVIN supply and 10µF capacitor for SVIN pin.
EN/DLY
This pin is internally fed with a 1µA current source to
SVIN. A delayed turn on is implemented by adding a
capacitor to this pin. The delay is proportional to the
capacitor value. The internal circuits are held off until
EN/DLY reaches the enable threshold of 1.24V.
RC
RC pin allows the slew rate of the output voltage to be
programmed by the addition of a capacitor from RC pin
to ground. RC pin is internally fed with a 1µA current
source and V_OUT slew rate is proportional to the
capacitor and the 1µA source. The RC pin cannot be left
floating. Use a minimum capacitor value of 120pF or
longer.
DELAY
Adding a capacitor to this pin allows the delay of the
POR signal.
When V_OUT reaches 90% of its nominal voltage, the
DELAY pin current source (1µA) starts to charge the
external capacitor. At 1.24V, POR is asserted high.
COMP
The MIC22950 uses an internal-compensation network
containing a fixed-frequency zero (phase-lead response)
and pole (phase-lag response) which allows the external
compensation network to be much simplified for stability.
The addition of a single capacitor and resistor will add
the necessary pole and zero for voltage-mode loop
stability using low-value, low-ESR ceramic capacitors.
MIC22950
FB
The FB pin provides the control path to control the
output. A resistor divider connecting the feedback to the
output is used to adjust the desired output voltage. Refer
to the feedback section in Applications Information of
this data sheet for more detail.
POR/PG
This is an open drain output. A 47k resistor can be used
for a pull-up to this pin. POR/PG is asserted high when
output voltage reaches 90% of nominal set voltage and
after the delay set by C_DELAY. POR/PG is asserted low
without delay when enable is set low or when the output
goes below the −10% threshold. For a power-good (PG)
function, the delay can be set to a minimum. This can be
done by removing the DELAY pin capacitor.
CF
This pin allows the setting of the switching frequency. A
200µA source current charges the capacitor on this pin
up to a voltage of 1V. At this point, CF pin capacitor is
then discharged with an internal N-Channel MOSFET
marking the end of the switching period. The capacitor
should be connected very close to the IC and grounded
directly to the SGND pin.
SW
This is the connection to the source of the internal P-
channel MOSFET and drain of the N-Channel MOSFET.
This is a high-frequency, high-power connection;
therefore, traces should be kept as short and as wide as
practical.
SGND
Internal signal ground for all low-power sections.
PGND
Internal ground connection to the source of the internal
N-Channel MOSFETs.
February 2010
9
M9999-021910-B