MIC2341 Datasheet, PDF (8/32 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

Micrel, Inc.
MIC2341/2341R
Pin Description (cont.)
Pin Number
47
40
46
38
17
33
45
7
18
19
20
30
Pin Name
/DLY_PWRGDA
/DLY_PWRGDB
SYSPWRGD
/INT
AGND
Pin Function
/DLY_PWRGD[A/B] are open-drain, asserted active-LOW digital outputs that are
normally connected by an external 10kΩ pull-up resistor (each) to VSTBY or to a
local logic supply. Each output signal is asserted approximately 164 ms after
their respective /PWRGD[A/B] output signals are asserted. The
/DLY_PWRGD[A/B] output signals are de-asserted when the /PWRGD[A/B]
outputs are de-asserted or upon a high-to-low transition on the ON[A/B] or
AUXEN[A/B] inputs. There is approximately a 1-ms delay between the de-
assertion of /DLY_PWRGD[A/B] and its corresponding /PWRGD[A/B] digital
outputs. Please consult the /PWRGD[A/B] and /DLY_PWRGD[A/B] state
diagrams within the Applications Information section for more detail.
System Power is Good. SYSPWRGD is an open-drain, active-HIGH digital
output that is normally connected by an external 10kΩ pull-up resistor to VSTBY
or to a local logic supply. The SYSPWRGD output signal is asserted LOW when:
(1) /CRSW[A] is asserted, ON[A] is asserted, /FORCE_ON_A is HIGH, and
either MAIN 12V[A] or MAIN 3V[B] output is below its output Power-Good
threshold;
(2) /CRSW[B] is asserted, ON[B] is asserted, /FOCRE_ON_B is HIGH, and
either MAIN 12V[B] or MAIN 3V[B] output is below its output Power-Good
threshold;
(3) /CRSW[A] is asserted, AUXEN[A] is asserted, /FORCE_ON_A is HIGH, and
the VAUXA output is below its output Power-Good threshold; or
(4) /CRSW[B] is asserted, AUXEN[B] is asserted, /FORCE_ON_B is HIGH, and
VAUXB output is below its Power-Good threshold.
For all other conditions, the SYSPWRGD output is open-drain. For more
information with respect to the SYSPWRGD output signal, please consult the
“Functional Description” section.
Interrupt Output: This open-drain, asserted active-LOW digital output is normally
connected by an external 10kΩ resistor to VSTBY or a local logic supply. This
signal is asserted whenever a power fault is detected. Checking the status of
/FAULT_MAIN[A/B] or /FAULT_AUX[A/B] output will determine which slot and
which rail caused the interrupt. To de-assert this signal output, please follow
instructions provided on /FAULT_MAIN[A/B] and /FAULT_AUX[A/B] output pin
descriptions.
3 Pins, IC Ground Connections: Tie directly to the system’s analog GND plane
directly at the device.
NC
Reserved: Make no external connections to these pins.
October 2007
8
M9999-102507-A
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