MIC2341 Datasheet, PDF (18/32 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

Micrel, Inc.
Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying
live supply voltages (“hot-plugged”), high inrush currents
often result due to the charging of bulk capacitance that
resides across the circuit board’s supply pins. This
transient inrush current can cause the system’s supply
voltages to temporarily go out of regulation, causing data
loss or system lock-up. In more extreme cases, the
transients occurring during a hot-plug event may cause
permanent damage to connectors or on-board
components.
The MIC2341 addresses these issues by limiting the
inrush currents to the load (PCI Express Board), and
thereby controlling the rate at which the load’s circuits
turn-on. In addition to this inrush current control, the
MIC2341 offers input and output voltage supervisory
functions and current limiting to provide robust protection
for both the system and circuit board.
System Interface
The MIC2341 employs a hardware system interface that
includes: ON[A/B], AUXEN[A/B], /CRSW[A/B],
/FAULT_MAIN[A/B], /FAULT_AUX[A/B], /PWRGD[A/B],
/INT, and SYSPWRGD.
Power-On Reset
VSTBY[A/B] are the main power supply for the
MIC2341’s internal logic circuits and state machines .
VSTBY[A/B] is required for proper operation of the
MIC2341’s internal logic circuitry and must be applied at
all times. A Power-On Reset (POR) cycle is initiated
after VSTBY[A/B] is higher than its V_UVLO(STBY) threshold
voltage and remains valid at that voltage for at least
80µs. All internal logic flags are cleared after POR. If the
VSTBY[A/B] pin voltages are cycled ON-OFF-ON, a
new power-on-reset cycle is initiated. V_STBY must be the
first supply input applied followed by the MAIN supply
inputs of 12V_IN and 3V_IN. During t_POR, all outputs remain
off. In most applications, the total POR interval will
consist of the time required to charge the V_STBY input
(bypass) capacitance to the UVLO threshold plus the
internal t_POR delay time. The following equation is used
to approximate the total POR interval:
( ) _{tPOR_TOTAL(µs)}
=
⎪⎨⎧⎢⎡
⎪⎩⎢⎣
C_STBY(µF) × V_ULVO(STBY)
I_CHARGE(STBY)(A)
⎤
⎥
×
10^−6
⎪⎫
⎬
+
t_POR
(µs)
⎥⎦
⎪⎭
where C_STBY is the V_STBY input bulk bypass capacitance
and I_CHARGE(STBY) is the current supplied by the V_STBY
source to charge the capacitance.
MIC2341/2341R
+12VOUT[A/B] and +3VOUT[A/B] Start-Up Cycles
All four of the MIC2341’s +12V and +3V gate drive
circuits have been designed to drive the gates of
external power MOSFETs. The +12V gate drive circuits
have been designed to drive P-channel MOSFETs and
the +3V gate drive circuits are intended to drive N-
channel MOSFETs. A list of recommended N- and P-
channel power MOSFETs suited for use with the
MIC2341 and PCI Express applications can be found in
Table 2.
These gate drive circuits have also been designed to
limit inrush current in one of two modes: (1) by
controlling the 12VGATE[A/B] or the 3VGATE[A/B]
voltage slew rates (dV_12GATE[A/B]/dt or dV_3GATE[A/B]/dt) or (2)
by actively limiting the inrush current, thereby charging
the corresponding load capacitance in current limit. The
mode that the MIC2341 automatically enters is
dependent upon the magnitude of the inrush current and
the magnitude of the load capacitance at 12VOUT[A/B]
and 3VOUT[A/B].
Mode 1: [12V/3V]GATE[A/B] Slew Rate Control
When a slot’s MAIN supply voltages (12VOUT[A/B] and
3VOUT[A/B]) are OFF, each of the 12VGATE[A/B] pins
is held at 12VIN[A/B] by an internal pull-up transistor.
Similarly, each 3VGATE[A/B] pin is internally held at
AGND. When the MAIN supply voltages are enabled by
a low-to-high transition on the ON[A/B] input pins (recall
that the /CRSW[A/B] inputs must also be asserted), the
12VGATE[A/B] and the 3VGATE[A/B] pins are each
connected to an internal constant current supply,
typically 25 µA each. At each 12VGATE[A/B] pin, this
constant current supply is a current sink; at each
3VGATE[A/B] pin, the supply is a current source. For
applications where the inrush current is controlled by the
12VGATE[A/B] voltage rate of change, an expression
for the circuit’s behavior is given by the following
equation:
dV_{12VGATE[A/ B] =} I_{GATE(12VGA TE) = 25µA}
dt
C_ISSP
C_ISSP
where C_ISSP = P-channel power MOSFET gate input
capacitance.
For example, a Si4435BDY (a 30-V P-channel power
MOSFET) exhibits an approximate C_ISSP of 1700pF at
V_DS = 12V. The 12VGATE[A/B] pin voltage rate-of-
change (slew rate) would be:
dV_{12VGATE[A/B] =} I_{GATE(12VSNK) = 25µA = 14.7 V}
dt
C_ISSP
1700pF
ms
The 12VOUT[A/B] inrush current to the load while the
12VGATE[A/B] voltage is ramping is dependent on
C_{LOAD(12VOUT[A/B])} and C_ISSP. An expression for the
12VOUT[A/B] inrush current is given by:
October 2007
18
M9999-102507-A
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