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KSZ8893FQL Datasheet, PDF (79/117 Pages) Micrel Semiconductor – Single-Chip 3-Port Switch with Fiber Support
Micrel, Inc.
TS-1000 Media Converter Registers
Register 64 (0x40): PHY Address
Bit Name
R/W
7-5 Number of Indication
R/W
OAM frame(s)
4 Addr4
R/W
3 Addr3
R/W
2 Addr2
R/W
1 Addr1
R/W
0 Addr0
R/W
Description
Set the number of Indication OAM frame(s) to be transmitted
for a single OAM status change. This setting is applicable to
only the following three OAM frames: Indicate Center MC
Condition, Indicate Terminal MC Condition, and Loop Mode
Stop Indication.
000 : send 1 OAM frame
001 : send 2 OAM frames
010 : send 3 OAM frames
011 : send 4 OAM frames
100 : send 5 OAM frames
101 : N/A
110 : N/A
111 : N/A
These 5-bits set the PHY addresses for port 1 and port 2.
00000 : N/A
00001 : Port 1 PHY address is 0x1
00010 : Port 1 PHY address is 0x2
…
11101 : Port 1 PHY address is 0x29
11110 : N/A
11111 : N/A
Port 2 PHY address = (Port 1 PHY address) + 1
Note:
In Center side MC mode (pins MCHS,MCCS] = [0,1]), a write
to these bits with port 1’s PHY address is required to enable
port 1 and start the Center side MC.
KSZ8893FQL
Default
000
0
0
0
0
1
Register 65 (0x41): Center Side Status
Bit Name
7 BUSY
6 Vendor mode
5-3 Reserved
2 Option b
1 Option a
0 Request
R/W Description
RO 1 = Indicate MC loop back mode in progress, or receive reply
frame/timeout is pending
0 = Exclude the above situations
R/W 1 = Non special vendor mode
0 = Special vendor mode (compare My & LNK Partner Vendor
Info = 0x009099h)
RO Reserved
Do not change the default values.
R/W 1 = Clear status bits S6 to S10 to zero on Terminal MC side
0 = Normal operation – supporting option b
R/W 1 = Disable “Indicate Center MC Condition” frame
0 = Enable “Indicate Center MC condition” frame
RO 1 = indicate change of status/value in registers # 0x50h,
0x51h, 0x58h, 0x59h, 0x5Dh, 0x5Eh, 0x5Fh. This bit is self-
cleared after a read.
0 = exclude the above situations
Note: This register is managed by the Center side.
Default
0
0
000
0
0
0
October 2007
79
M9999-101607-1.3