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KSZ8893FQL Datasheet, PDF (103/117 Pages) Micrel Semiconductor – Single-Chip 3-Port Switch with Fiber Support | |||
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Micrel, Inc.
KSZ8893FQL
Examples:
1. MIB Counter Read (Read port 1 âRx64Octetsâ Counter)
Write to reg. 121 (0x79) with 0x1c
// Read MIB counters selected
Write to reg. 122 (0x7A) with 0x0e
// Trigger the read operation
Then
Read reg. 128 (0x80), overflow bit [31]
// If bit 31 = 1, there was a counter overflow
valid bit [30]
// If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
2. MIB Counter Read (Read port 2 âRx64Octetsâ Counter)
Write to reg. 121 (0x79) with 0x1c
// Read MIB counter selected
Write to reg. 122 (0x7A) with 0x2e
// Trigger the read operation
Then,
Read reg. 128 (0x80), overflow bit [31]
// If bit 31 = 1, there was a counter overflow
valid bit [30]
// If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
3. MIB Counter Read (Read âPort1 TX Drop Packetsâ Counter)
Write to reg. 121 (0x79) with 0x1d
// Read MIB counter selected
Write to reg. 122 (0x7A) with 0x00
// Trigger the read operation
Then
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Additional MIB Counter Information
âPer Portâ MIB counters are designed as âread clear.â These counters will be cleared after they are read.
âAll Port Dropped Packetâ MIB counters are not cleared after they are accessed and do not indicate overflow or validity;
therefore, the application must keep track of overflow and valid conditions.
To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are 160
registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2 minutes.
It is recommended that the software read all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.
October 2007
103
M9999-101607-1.3
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