KSZ8841_11 Datasheet, PDF (75/105 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with Non-PCI Interface

Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Bank 42 Indirect Access Control Register (0x00): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read or write access is
determined by register bit 12).
Bit
Default
R/W Description
15-13 0x0
12
0
11-10 0x0
9-0
0x000
RW Reserved.
RW Read High. Write Low
1 = read cycle.
0 = write cycle.
RW Table Select
00 = reserved.
01 = reserved.
10 = reserved.
11 = MIB counter selected.
RW Indirect Address
Bit 9-0 of indirect address.
Bank 42 Indirect Access Data Register 1 (0x02): IADR1
This register contains the indirect data for the chip function.
Bit
Default
R/W Description
15-0
0x0000
RO Reserved.
Bank 42 Indirect Access Data Register 2 (0x04): IADR2
This register contains the indirect data for the chip function.
Bit
Default
R/W Description
15-0
0x0000
RO Reserved.
Bank 42 Indirect Access Data Register 3 (0x06): IADR3
This register contains the indirect data for the chip function.
Bit
Default
R/W Description
15-0
0x0000
RO Reserved.
Bank 42 Indirect Access Data Register 4 (0x08): IADR4
This register contains the indirect data for the chip function.
Bit
Default
R/W Description
15-0
0x0000
RW Indirect Data
Bit 15-0 of indirect data.
Bank 42 Indirect Access Data Register 5 (0x0A): IADR5
This register contains the indirect data for the chip function.
Bit
15-0
Default
0x0000
R/W Description
RW Indirect Data
Bit 31-16 of indirect data.
Bank 43– 44: Reserved
Except Bank Select Register (0xE)
October 2007
75
M9999-102207-1.6