KSZ8873MLLJ Datasheet, PDF (71/108 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8873MLLJ
Register 111 (0x6F): TOS Priority Control Register 15
Bit
Name
R/W Description
The value in this field is used as the frame’s priority when
7-6
DSCP[127:126] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3F.
The value in this field is used as the frame’s priority when
5-4
DSCP[125:124] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3E.
The value in this field is used as the frame’s priority when
3-2
DSCP[123:122] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3D.
The value in this field is used as the frame’s priority when
1-0
DSCP[121:120] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3C.
Default
00
00
00
00
Registers 112 to 117
Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address is used as the Source Address for the
MAC’s full duplex flow control (PAUSE) frame.
Register 112 (0x70): MAC Address Register 0
Bit
Name
R/W Description
7-0
MACA[47:40] R/W
Default
0x00
Register 113 (0x71): MAC Address Register 1
Bit
Name
R/W Description
7-0
MACA[39:32] R/W
Default
0x10
Register 114 (0x72): MAC Address Register 2
Bit
Name
R/W Description
7-0
MACA[31:24] R/W
Default
0xA1
Register 115 (0x73): MAC Address Register 3
Bit
Name
R/W Description
7-0
MACA[23:16] R/W
Default
0xFF
Register 116 (0x74): MAC Address Register 4
Bit
Name
R/W Description
7-0
MACA[15:8]
R/W
Default
0xFF
Register 117 (0x75): MAC Address Register 5
Bit
Name
R/W Description
7-0
MACA[7:0]
R/W
Default
0xFF
September 2011
71
M9999-091911-1.8