KSZ8873MLLJ Datasheet, PDF (52/108 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8873MLLJ
Register 6 (0x06): Global Control 4
Bit
Name
7
Reserved
R/W Description
RO
Reserved
Do not change the default values.
6
Port 3 Duplex
Mode
Selection
R/W
=1, Enable Port 3 MII to half-duplex mode.
=0, Enable Port 3 MII to full-duplex mode.
5
Port 3 Flow
Control Enable
R/W
=1, Enable full duplex flow control on Switch port 3 MII interface.
=0, Disable full duplex flow control on Switch port 3 MII interface.
4
Port 3 Speed
selection
R/W
=1, The port 3 MII switch interface is in 10Mbps mode
=0, The port 3 MII switch interface is in 100Mbps mode
3
Null VID
Replacement
R/W
=1, Will replace NULL VID with port VID (12 bits)
=0, No replacement for NULL VID
2-0
Broadcast
Storm
Protection
Rate⁽¹⁾
This register along with the next register determines how many “64
R/W
byte blocks” of packet data are allowed on an input port in a preset
period. The period is 67ms for 100BT or 500ms for 10BT. The
default is 1%.
Bit [10:8]
Default
0
0
Pin P1LED0 strap
option.
Pull-up(1): Half -duplex
mode
Pull-down(0): Full-
duplex mode (default)
Note: P1LED0 has
internal pull-down.
1
Pin P1LED1 strap
option.
Pull- up(1): Enable
flow control
Pull-down(0): Disable
flow control
Note: P1LED1 has
internal pull-up.
0
Pin P3SPD strap
option.
Pull-up(1): Enable
10Mbps
Pull-down(0): Enable
100Mbps (default)
Note: P3SPD has
internal pull-down.
0
000
Register 7 (0x07): Global Control 5
Bit
Name
R/W Description
Broadcast
Storm
This register along with the previous register determines how many
7-0
Protection
Rate⁽¹⁾
R/W
“64 byte blocks” of packet data are allowed on an input port in a
preset period. The period is 67ms for 100BT or 500ms for 10BT.
The default is 1%.
Bit [7:0]
Note: ⁽¹⁾ 100BT Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63
Default
0x63
September 2011
52
M9999-091911-1.8