PL602031UMG Datasheet, PDF (7/9 Pages) Micrel Semiconductor – HCSL-Compatible Clock Generator for PCI Express

Micrel, Inc.
PL60203X
PCB Layout Considerations for Performance Optimization
The following guidelines are designed to assist you with a performance-optimized PCB design:
 Keep all the PCB traces to PL60203X as short as
possible. Also keep all other traces as far away
from PL60203X as possible.
 Place the crystal as close as possible to both
crystal pins of the device. This will reduce the
cross-talk between the crystal and the other
signals.
 Separate crystal pin traces from the other signals
on the PCB, but allow ample distance between the
two crystal pin traces.
 Place a 0.01µF decoupling capacitor between
VDD and GND on the component side of the PCB,
close to the VDD pin. It is not recommended to
place this component on the backside of the PCB.
 It is highly recommended to keep the VDD and
GND traces as short as possible.
 When connecting long traces (>1 inch) to a CMOS
output, it is important to design the traces as a
transmission line, or “stripline”, to avoid reflections
or ringing. In this case, the CMOS output needs to
be matched to the trace impedance. Usually,
“striplines” are designed for 50Ω impedance and
CMOS outputs usually have an impedance of less
than 50Ω, so matching can be achieved by adding
a resistor in series with the CMOS output pin to
the “stripline” trace.
Power Supply Filtering Recommendations
Preferred filter, using Micrel MIC94300 or MIC94310 Ripple Blocker™:
Alternative, traditional filter, using a ferrite bead:
December 11, 2013
7
Revision 1.1
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