PL602031UMG Datasheet, PDF (3/9 Pages) Micrel Semiconductor – HCSL-Compatible Clock Generator for PCI Express

Micrel, Inc.
Pin Configuration
PL60203X
Pin Description
Pin Number
1
2
3, 4
5
6, 7
10
Pin Name
XIN, FIN
GND0
CLK0[0:1]
VDD0
CLK1[0:1]
VDD1
11
OE1
12
GND1
15
XOUT
16
OE0
8, 9
13, 14
DNC
ePad
16-Pin QFN (Top View)
Pin Type
I
I
O
P
O
P
I
P
O
I
Pin Function
Crystal input pin or reference clock input.
GND connection for CLK0.
Differential clock output pair
VDD connection for CLK0
Differential clock output pair
VDD connection for CLK1
Output enable pin for CLK1. High=Enabled, Low=Disabled. OE1 has a
60KΩ pull-up resistor.
GND connection for CLK1
Crystal output pin
Output enable pin for CLK0. High=Enabled, Low=Disabled. OE0 has a
60KΩ pull-up resistor.
Do not connect.
Center pad for thermal relief. Connect to GND.
December 11, 2013
3
Revision 1.1
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