MIC59P50_15 Datasheet, PDF (6/12 Pages) Micrel Semiconductor – 8-Bit Parallel-Input Protected Latched Driver

Micrel, Inc.
Timing Diagram
MIC59P50
Timing Conditions
T_A = +25°C; Logic levels are V_DD and V_SS; V_DD = 5V.
A. Minimum data active time before strobe enabled (data set-up time)
B. Minimum data active time after strobe disabled (data hold time)
C. Minimum strobe pulse width
D. Typical time between strobe activation and output on-to-off transition
E. Typical time between strobe activation and output off-to-on transition
F. Minimum clear pulse width
G. Minimum data pulse width
50ns
50ns
125ns
500ns
500ns
300ns
225ns
July 29, 2015
6
Revision 2.0