KSZ8893M Datasheet, PDF (51/116 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8893MQL/MBL
I²C Slave Serial Bus Configuration
In managed mode, the KSZ8893MQL/MBL can be configured as an I²C slave device. In this mode, an I²C master
device (external controller/CPU) has complete programming access to the KSZ8893MQL/MBL’s 142 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect
access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and
counters are indirectly accessed via registers 121 to 131.
In I²C slave mode, the KSZ8893MQL/MBL operates like other I²C slave devices. Addressing the
KSZ8893MQL/MBL’s 8-bit registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations.
Details of I²C read/write operations and related timing information can be found in the AT24C02 Datasheet.
Two fixed 8-bit device addresses are used to address the KSZ8893MQL/MBL in I²C slave mode. One is for read;
the other is for write. The addresses are as follow:
1011_1111 <read>
1011_1110 <write>
The following is a sample procedure for programming the KSZ8893MQL/MBL using the I²C slave serial bus:
1. Enable I²C slave mode by setting the KSZ8893MQL/MBL strap-in pins PS[1:0] (pins 100 and 101,
respectively) to “01”.
2. Power up the board and assert reset to the KSZ8893MQL/MBL. After reset, the “Start Switch” bit (register 1
bit [0]) is set to ‘0’.
3. Configure the desired register settings in the KSZ8893MQL/MBL, using the I²C write operation.
4. Read back and verify the register settings in the KSZ8893MQL/MBL, using the I²C read operation.
5. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893MQL/MBL with the programmed settings.
Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
SPI Slave Serial Bus Configuration
In managed mode, the KSZ8893MQL/MBL can be configured as a SPI slave device. In this mode, a SPI master
device (external controller/CPU) has complete programming access to the KSZ8893MQL/MBL’s 142 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect
access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and
counters are indirectly accessed via registers 121 to 131.
The KSZ8893MQL/MBL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for
data write. SPI multiple read and multiple write are also supported by the KSZ8893MQL/MBL to expedite register
read back and register configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8893MQL/MBL SPIS_N input pin
(SPI Slave Select signal) low after a byte (a register) is read. The KSZ8893MQL/MBL internal address counter
increments automatically to the next byte (next register) after the read. The next byte at the next register address
is shifted out onto the KSZ8893MQL/MBL SPIQ output pin. SPI multiple read continues until the SPI master
device terminates it by de-asserting the SPIS_N signal to the KSZ8893MQL/MBL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8893MQL/MBL SPIS_N
input pin low after a byte (a register) is written. The KSZ8893MQL/MBL internal address counter increments
automatically to the next byte (next register) after the write. The next byte that is sent from the master device to
the KSZ8893MQL/MBL SDA input pin is written to the next register address. SPI multiple write continues until the
SPI master device terminates it by de-asserting the SPIS_N signal to the KSZ8893MQL/MBL.
For both SPI multiple read and multiple write, the KSZ8893MQL/MBL internal address counter wraps back to
register address zero once the highest register address is reached. This feature allows all 142
KSZ8893MQL/MBL registers to be read, or written with a single SPI command from any initial register address.
The KSZ8893MQL/MBL is capable of supporting a 5MHz SPI bus.
February 2010
51
M9999-021110-1.6