KSZ8864RMN Datasheet, PDF (47/112 Pages) Micrel Semiconductor – Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces

Micrel, Inc.
KSZ8864RMN
SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’.
The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit
[4:0]}. TA is turn-around bits. TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from
output mode and the followed ‘0’ is the read response from device, as the switch configuration registers are 8-bit
wide, only the lower 8 bits of data bits [15:0] are used
SMI register Write access is selected when OP Code is set to “01” and bits [2:1] of the PHY address is set to ‘11’.
The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit
[4:0]}. TA bits [1:0] are set to ’10’, as the switch configuration registers are 8-bit wide, only the lower 8 bits of data bits
[15:0] are used.
To access the KSZ8864RMN registers 0-255 (0x00 – 0xFF), the following applies:
PHYAD [4, 3, 0] and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD [4,3,0], REGAD[4:0]}
= bits [7:0] of the 8-bit address.
Registers are eight data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write operation, data
bits [15:8] are not defined, and hence can be set to either 0s or 1s.
SMI register access is the same as the MIIM register access, except for the register access requirements presented
in this section.
September 2011
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M9999-092011-1.4