SM802112 Datasheet, PDF (4/12 Pages) Micrel Semiconductor – ClockWorks™ 3-Output, 480MHz/80MHz, Ultra-Low Jitter LVDS/CMOS Frequency Synthesizer

Micrel, Inc.
Absolute Maximum Ratings⁽¹⁾
Supply Voltage (V_DD, V_DDO1/2) ......................................+4.6V
Input Voltage (V_IN) .............................. −0.50V to V_DD + 0.5V
Lead Temperature (soldering, 20s)............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (T_s) ......................... −65°C to +150°C
SM802112
Operating Ratings⁽²⁾
Supply Voltage (V_DD, V_DDO1/2)............ +2.375V to +3.465V
Ambient Temperature (T_A).......................–40°C to +85°C
Junction Thermal Resistance⁽³⁾
QFN (θ_JA)
Still-Air......................................................24°C/W
QFN (ψ_JB)
Junction-to-Board ......................................8°C/W
DC Electrical Characteristics⁽⁴⁾
V_DD = V_DDO1/2 = 3.3V ±5% or 2.5V ±5%
V_DD = 3.3V ±5%, V_DDO1/2 = 3.3V ±5% or 2.5V ±5%
T_A = −40°C to +85°C.
Symbol
Parameter
Condition
V_DD, V_DDO1/2 2.5V Operating Voltage
V_DD, V_DDO1/2 3.3V Operating Voltage
I_DD
Supply current V_DD + V_DDO Outputs open
Min.
2.375
3.135
Typ.
2.5
3.3
125
Max.
2.625
3.465
Units
V
V
158
mA
LVDS DC Electrical Characteristics⁽⁴⁾
V_DD = V_DDO1/2 = 3.3V ±5% or 2.5V ±5%
V_DD = 3.3V ±5%, V_DDO1/2 = 3.3V ±5% or 2.5V ±5%
T_A = −40°C to +85°C. R_L = 100Ω across Q and /Q.
Symbol Parameter
Condition
V_OD
Differential Output Voltage
Figures 1, 4
ΔV_OD
V_OD Magnitude Change
V_OS
Offset Voltage
ΔV_OS
V_OS Magnitude Change
Min.
275
1.15
Typ.
350
1.25
Max.
475
40
1.50
50
Units
mV
mV
V
mV
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
4. The circuit is designed to meet the AC and DC specifications shown in the above table(s) after thermal equilibrium has been established.
September 2011
4
M9999-091411-A
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