MIC502_11 Datasheet, PDF (4/15 Pages) Micrel Semiconductor – Fan Management IC

Micrel, Inc.
MIC502
Symbol Parameter
Condition
Min Typ Max Units
Overtemperature Fault Output
V_OL
Active (Low) Output Voltage
I_OL = 2mA
0.3
V
I_OH
Off-State Leakage
V_/OTF = V_DD
1
µA
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Part is functional over this V_DD range; however, it is characterized for operation at 4.5V ≤ V_DD ≤ 5.5V and 10.8V ≤ V_DD ≤ 13.2V ranges. These ranges
correspond to nominal V_DD of 5V and 12V, respectively.
5. Guaranteed by design.
6. V_OT is guaranteed by design to always be higher than V_PWM(max).
7.
Logic time base and PWM frequency. For other values of C_F, f(Hz) = 30Hz
0.1µF _{, where C is in µF.}
C
Timing Diagrams
V_{O T}
0.7V_DD
V_{T 1}
V_{T 2}
V_{S L P}
0.3V_DD
V_IH
V_IL
0V
50%
80%
40%
70%
40%
100%
Input
Signal
Range
30%
0%
V_{O T F}
V_{O H}
V_{O L}
0V
V_{O U T}
A
V_{O H}
V_{O L}
0V
t_{P W M}
50%
B
C
D
E
80%
40%
70%
0%
F
t_{S T A R T U P}
G
100%
40%
Output
Duty Cycle
Figure 1. Typical System Behavior
Note A.
Note B.
Note C.
Note D.
Note E.
Note F.
Note G.
Output duty-cycle is initially determined by V_T1, as it is greater than V_T2.
PWM duty-cycle follows V_T1 as it increases.
V_T1 drops below V_T2. V_T2 now determines the output duty-cycle.
The PWM duty-cycle follows V_T2 as it increases.
Both V_T1 and V_T2 decrease below V_SLP but above VIL. The device enters sleep mode.
The PWM ‘wakes up’ because one of the control inputs (V_T1 in this case) has risen above V_WAKE. The startup timer is triggered, forcing OUT
high for 64 clock periods. (V_WAKE = V_SLP + V_HYST. See “Electrical Characteristics”).
Following the startup interval, the PWM duty-cycle is the higher of V_T1 and V_T2.
November 2006
4
M9999-112206