KSZ8842-16 Datasheet, PDF (34/126 Pages) Micrel Semiconductor – 2-Port Ethernet Switch with Non-PCI Interface

Micrel Confidential
KSZ8842-16/32 MQL/MVL
ISA
EISA
Non-burst
Glue Logic
Glue Logic
KSZ8842M BIU
No Addr Latch
(ADSN = 0)
Address Latch
Central decode
Local
decode
Asynchronous
Interface
Burst
VLBus
Glue Logic
Glue Logic
Central decode
(VLBUSN = 1)
Address Latch
Local
decode
(VLBUSN = 0)
Synchronous
Interface
Note: To use DATACSN & 32-bit only for Central decode
Figure 11. Mapping from ISA-like, EISA-like, and VLBus-like transactions to the KSZ8842M Bus
HA[1]
HA[15:2]
HD[7:0]
KSZ8842-16
A[1]
A[15:2]
D[7:0]
D[15:8]
HA[1]
HA[15:2]
HD[7:0]
HD[15:8]
KSZ8842-16
A[1]
A[15:2]
D[7:0]
D[15:8]
GND
HA[15:2]
HD[7:0]
HD[15:8]
HD[23:16]
HD[31:24]
KSZ8842-32
A[1]
A[15:2]
D[7:0]
D[15:8]
D[23:16]
D[31:24]
HA[0]
VDD
BE0N
BE1N
HA[0]
nSBHE
BE0N
BE1N
nHBE[0]
nHBE[1]
nHBE[2]
nHBE[3]
BE0N
BE1N
BE2N
BE3N
8-bit Data Bus
16-bit Data Bus
(for example: ISA-like)
32-bit Data Bus
(for example: EISA-like)
Figure 12. KSZ8842M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections
BIU Implementation Principles
Since the KSZ8842M is an I/O device with 16 addressable locations, address decoding is based on the values of A15-A4
and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is
assumed (BE3N – BE0N are ignored).
If address latching is required, the address is latched on the rising edge of ADSN and is transparent when ADSN=0.
1. Byte, word, and double-word data buses and accesses (transfers) are supported.
November 2005
34
Rev. 1.4