MIC3000 Datasheet, PDF (31/68 Pages) Micrel Semiconductor – SFP Management IC

MIC3000
Serial Port Operation
The MIC3000 uses standard Write_Byte, Read_Byte, and
Read_Word operations for communication with its host. It
also supports Page_Write and Sequential_Read transac-
tions. The Write_Byte operation involves sending the device’s
slave address (with the R/W bit low to signal a write opera-
tion), followed by the address of the register to be operated
upon and the data byte. The Read_Byte operation is a
composite write and read operation: the host first sends the
device’s slave address followed by the register address, as in
a write operation. A new start bit must then be sent to the
MIC3000, followed by a repeat of the slave address with the
R/W bit (LSB) set to the high (read) state. The data to be read
from the part may then be clocked out. A Read_Word is
similar, but two successive data bytes are clocked out rather
than one. These protocols are shown in Figure 21 to 24.
The MIC3000 will respond to up to four sequential slave
addresses depending upon whether it is in OEM or User
mode. A match between one of the MIC3000’s addresses
and the address specified in the serial bit stream must be
made to initiate communication. The MIC3000 responds to
slave addresses A0_h and A2_h in User Mode; it also responds
to A4_h and A6_h in OEM Mode (assuming I2CADR = Ax_h).
Micrel
Page Writes
To increase the speed of multi-byte writes, the MIC3000
allows up to four consecutive bytes (one page) to be written
before the internal write cycle begins. The entire non-volatile
memory array is organized into four-byte pages. Each page
begins on a register address boundary where the last two bits
of the address are 00_b. Thus the page is composed of any four
consecutive bytes having the addresses xxxxxx00_b,
xxxxxx01_b, xxxxxx10_b, and xxxxxx11_b.
The page write sequence begins just like a Write_Byte
operation with the host sending the slave address, R/W bit
low, register address, etc. After the first byte is sent the host
should receive an acknowledge. Up to three more bytes can
be sent in sequence. The MIC3000 will acknowledge each
one and increment its internal address register in anticipation
of the next byte. After the last byte is sent, the host issues a
STOP. The MIC3000’s internal write process then begins. If
more than four bytes are sent, the MIC3000’s internal ad-
dress counter wraps around to the beginning of the four-byte
page.
To accelerate calibration and testing, NVRAM write cycles
can be disabled completely by setting the WRINH bit in
OEMCAL0. Writes to registers that do not have NVRAM
backup will not incur write-cycle delays when writes are
inhibited. Write operations on registers that exist only in
NVRAM will still incur write cycle delays.
MIC3000 Slave Address
Register Address
Data Byte to MIC3000
DATA S 1 0 1 0 0 0 0 0 A X X X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 /A P
START
R/W = WRITE
ACKNOWLEDGE
ACKNOWLEDGE
NOT ACKNOWLEDGE
STOP
CLK
Master to slave transfer,
i.e., DATA driven by master.
Slave to master transfer,
i.e., DATA driven by slave.
Figure 21. Write Byte Protocol
MIC3000 Slave Address
Register Address
MIC3000 Slave Address Data Read From MIC3000
DATA S 1 0 1 0 0 0 0 0 A 0 0 X X X X X X A S 1 0 0 1 X X A0 1 A X X X X X X X X /A P
START
R/W = WRITE
ACKNOWLEDGE
ACKNOWLEDGE
START
R/W = READ
ACKNOWLEDGE NOT ACKNOWLEDGE
STOP
CLK
Master to slave transfer,
i.e., DATA driven by master.
Slave to master transfer,
i.e., DATA driven by slave.
Figure 22. Read Byte Protocol
MIC3000 Slave Address
Register Address
MIC3000 Slave Address
High-Order Byte
from MIC3000
Low-Order Byte
from MIC3000
DATA S 1 0 1 0 0 0 0 0 A 0 0 0 0 0 0 X X A S 1 0 1 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 /A P
START
R/W = WRITE
ACKNOWLEDGE
ACKNOWLEDGE
START
R/W = READ
ACKNOWLEDGE
ACKNOWLEDGE
NOT ACKNOWLEDGE
STOP
CLK
Master-to-slave tranfer,
i.e., DATA driven by master.
Slave-to-master transfer,
i.e.,DATA driven by slave.
Figure 23. Read_Word Protocol
October 2004
31
M9999-101204