KSZ8893MQLI Datasheet, PDF (30/116 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8893MQL/MBL
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver
circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is
separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with
short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input
exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8893MQL/MBL decodes a data
frame. The receiver clock is maintained active during idle periods in between data reception.
Power Management
The KSZ8893MQL/MBL features a per-port power down mode. To save power, a PHY port that is not in use can
be powered down via port control register, or MIIM PHY register.
In addition, there is a full chip power down mode. When activated, the entire chip is powered down.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8893MQL/MBL supports HP Auto
MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive
pairs for the KSZ8893MQL/MBL device. This feature is extremely useful when end users are unaware of cable
types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be
disabled through the port control registers, or MIIM PHY registers.
The IEEE 802.3u standard MDI and MDI-X definitions are:
MDI
RJ-45 Pins
1
2
3
6
Signals
TD+
TD-
RD+
RD-
MDI-X
RJ-45 Pins
Signals
1
RD+
2
RD-
3
TD+
6
TD-
Table 2. MDI/MDI-X Pin Definitions
February 2010
30
M9999-021110-1.6