MIC2790_14 Datasheet, PDF (3/18 Pages) Micrel Semiconductor – Supervisor with High-Accuracy, Ultra-Fast Propagation Delay, and Capacitor-Programmable Reset Delay

Micrel, Inc.
MIC2790/1/3
Pin Description
Pin
Number
TSOT-23
(6L)
Pin
Number
1.6 × 1.6
(6L)
1
6
1
6
2
5
3
4
4
3
5
2
6
1



EP
Pin
Number
2×2
(6L)
6
6
5
4
3
2
1

EP
Pin
Number
2×2
(8L)
7
8
6
5
4
3
2
1
EP
Pin
Name
Pin Function
/RESET
RESET
GND
/MR
CTH
SNS
VDD
EN
ePad
/RESET is an active-low output pin and is available in an open-
drain or push-pull configuration.
In the open-drain configuration, a pull-up resistor to VDD is
required and /RESET pin is asserted low when /MR is set to a
logic low or the SNS voltage decreases below the threshold
voltage. /RESET will remain low for the reset timeout delay after
SNS > (VTH + VHYST) and /MR is set to a logic high.
The push-pull configuration does not require a pull-up resistor and
behaves exactly the same as the open-drain configuration.
Reset is an active-high push-pull output and is asserted high when
/MR is set to a logic low or the SNS voltage decreases below the
threshold voltage. RESET will remain high for the reset timeout
delay after SNS > (VTH + VHYST) and /MR is set to a logic high.
Supply Ground.
Manual reset is an active-low input logic level pin and is internally
pulled to VDD through a 90kΩ pull-up resistor. Pulling the /MR
input to a logic low asserts RESET and /RESET pins. /RESET will
remain low and RESET will remain high for the reset timeout delay
after /MR is pulled to logic high.
Programmable timeout delay. Connect a capacitor to ground to set
a user defined reset delay time.
Voltage monitor input. Connect sense pin to the voltage to be
monitored through a resistor divider. When this voltage decreases
below the threshold voltage, VTH, /RESET is asserted low and
RESET is asserted high.
Supply voltage pin. Bypass with a 1µF capacitor from this pin to
GND.
Enable input function is only available in the MIC2793 version.
This pin enables the /MR input function and RESET and /RESET
outputs. When EN is in a logic low state, the reset outputs are de-
asserted. The EN pin has an internal 90kΩ pull-up resistor to VDD.
Exposed Pad. Connect to ground plane.
May 22, 2014
3
Revision 1.2