MIC2790_14 Datasheet, PDF (11/18 Pages) Micrel Semiconductor – Supervisor with High-Accuracy, Ultra-Fast Propagation Delay, and Capacitor-Programmable Reset Delay

Micrel, Inc.
Functional Description
Design and Product Advantages
The MIC2790/1/3 is a highly-accurate supervisor circuit
with an ultra-fast propagation delay of 2.2µs (maximum)
over the temperature range of 40˚C to +125˚C.
Additional features in the MIC2790/1/3 include a manual
reset input pin, a capacitor-programmable reset timeout
delay and both an active-low and active-high reset
output. The capacitor-programmable reset delay help
protect against accidental system glitch during a reset
timeout.
VDD
The input supply (V_DD) provides power to the
comparators and logic timers. V_DD operating range is
1.5V to 5.5V. A ceramic input capacitor of 1µF with a
minimum voltage rating of 6.3V is recommended between
VDD and GND. Refer to PCB Layout Recommendations
for details.
EN
The enable (EN) pin feature is only available in the
MIC2793 option and has an internal pull-up of 90kΩ
resistor to VDD. A logic high signal on EN pin enables the
reset logic outputs, while a logic low signal disables the
reset outputs. See Figure 3 in the Timing Diagrams
section for more information.
CTH
C_TH is a programmable timeout delay pin. Connect a
capacitor to ground to set a reset timeout delay ranging
from 1ms to 10s. Refer to the Reset Timeout Delay vs.
C_TH plot in the Typical Characteristics section for
examples.
SNS
The sense (SNS) input pin monitors the user’s voltage
through a resistor divider network as shown in Figure 5.
V_MONITOR
SNS = 0.4V
R_TOP
R_BOTTOM
MIC2790/1/3
To set R_TOP and R_BOTTOM, use Equation 1 and set an
arbitrary R_TOP value greater than 100kΩ and solve for
R_BOTTOM or vice versa.
V_{MONIT OR}
 0.4V  1 ^RTOP 
 ^RBOTTOM 
Eq. 1
GND
The ground (GND) pin is the return path for VDD, logic
gates, and output pins. Refer to PCB Layout
Recommendations for details.
/MR
Manual reset (/MR) is an active-low input pin that is
internally pulled to VDD with a 90kΩ resistor. When /MR
is asserted to a logic-low level, /RESET will transition to a
logic low state while RESET will transition to a logic high
state. See the Timing Diagrams section for more
information.
/RESET
/RESET is an active-low output and is available in two
output configurations: open-drain or push-pull. The open-
drain configuration requires an external pull-up resistor,
while the push-pull does not.
/RESET is asserted low when /MR is set to a logic-low or
the SNS voltage decreases below the threshold voltage.
/RESET will remain low for the programmed reset timeout
delay after SNS > (V_TH + V_HYST) and /MR is set to a logic-
high, and then /RESET will transition high to indicate
normal regulation. See the Timing Diagrams section for
more information.
RESET
RESET is an active-high push-pull output and is asserted
high when /MR is set to a logic low or the SNS voltage
decreases below the threshold voltage. RESET will
remain high for the programmed reset timeout delay after
SNS > (V_TH + V_HYST) and /MR is set to a logic high, and
then RESET will transition low to indicate normal
regulation. See the Timing Diagrams section for more
information.
Figure 5. Resistor Divider on SNS pin
May 22, 2014
11
Revision 1.2