MIC2155 Datasheet, PDF (26/33 Pages) Micrel Semiconductor – 2-Phase, Single Output, PWM Synchronous Buck Control IC

Micrel, Inc.
the snubber and diminishes its effectiveness.
A proper snubber design requires the parasitic
inductance and capacitance be known. A method of
determining these values and calculating the damping
resistor value is outlined below.
1. Measure the ringing frequency at the switch node
which is determined by parasitic L_P and C_P. Define this
frequency as f₁.
2. Add a capacitor C_S (normally at least 3 times as big as
the C_OSS of the FET) from the switch node to ground and
measure the new ringing frequency. Define this new
(lower) frequency as f₂. L_P and C_P can now be solved
using the values of f₁, f₂ and C_S.
3. Add a resistor R_S in series with C_S to generate critical
damping.
Step 1: First measure the ringing frequency on the
switch node voltage when the high-side MOSFET turns
on. This ringing is characterized by the equation:
f₁ = _2π
1
L_P × C_P
where C_P and L_P are the
parasitic capacitance and inductance
Step 2: Add a capacitor, C_S, in parallel with the
synchronous MOSFET, Q2. The capacitor value should
be approximately 3 times the C_OSS of Q2. Measure the
frequency of the switch node ringing, f₂
f₂ = _2π
1
Lp × (Cs + Cp)
Define f’ as:
f ^' = ^f1
f₂
Combining the equations for f₁, f₂ and f’ to derive C_P, the
parasitic capacitance
C_P
=
C_S
2 × (f ^' )²
−1
L_P is solved by re-arranging the equation for f₁.
L_P
=
(2π)²
1
× C_P
× (f₁)²
Step 3: Calculate the damping resistor.
Critical damping occurs at Q = 1
Q = ^{1 LP} = 1
R_S C_S
Solving for R_S
MIC2155/2156
R_S =
L_P
C_S
Figure 23 shows the snubber in the circuit and the
damped switch node waveform.
L_STRAY1
R_DS
L_STRAY2
L_STRAY3
R_S
C_OSS2
L_STRAY4
C_S
Figure 23. Snubber Circuit
The snubber capacitor, C_S, is charged and discharged
each switching cycle. The energy stored in C_S is
dissipated by the snubber resistor, R_S, two times per
switching period. This power is calculated in the
equation below.
P_SNUBBER = f_S × C_S × V_IN2
where:
f_S is the switching frequency for each phase
V_IN is the DC input voltage
Compensation of the Output Voltage Loop
The voltage regulation, filter and power stage section is
shown in Figure 24. The error amplifier for Channel 1 is
used to regulate the output voltage and compensate the
voltage regulation loop. It is a voltage output op amp that
is designed to use type III (PID) compensation. Type III
compensation has two compensating zeros, two poles
and a pole at the origin. The figure also shows the
transfer function for each section.
Compensation is necessary to insure the control loop
has adequate bandwidth and phase margin to properly
respond to input voltage and output current transients.
High gain at DC and low frequencies is needed for
accurate output voltage regulation. Attenuation near the
switching frequency prevents switching frequency noise
from interfering with the control loop.
May 2009
26
M9999-052709-A
[phone]