MIC2155 Datasheet, PDF (14/33 Pages) Micrel Semiconductor – 2-Phase, Single Output, PWM Synchronous Buck Control IC

Micrel, Inc.
C _VDD
10µF
C _BST
Figure 6. Emitter Follower Regulator
The internal VDD regulator can supply up to 75mA of
current to drive the external MOSFETs. Power
dissipation inside the MIC2155/6 control IC is divided
between power dissipated in the controller’s analog
circuitry and power dissipated in the drive circuitry. Drive
circuitry power is almost always much greater than
analog circuitry power. Total regulator power dissipation
is calculated using the following formula:
P_DISS = V_IN1 × I_IN1 = V_IN1 × (f_S × Qg + I_Q )
Where:
Qg = total gate charge of all MOSFETs
f_S = switching frequency of each stage (500kHz
for the MIC2155 and 300kHz for the MIC2156)
I_Q = Controller quiescent current (non-switching
supply current)
In some instances, power dissipation inside the control
IC may limit the controller’s maximum ambient
temperature. For example, if the MIC2155 is powered
from a 12V source and is driving 4 FETs. If each FET
has a Qg=37nC, the total power dissipation in the
MIC2155 is:
P_DISS = 12V × (37nC × 4) × 500kHz = 0.888W
The maximum operating ambient temperature is:
T_A(MAX) = T_J(MAX) − P_DISS × θ_JC
T_A(MAX) = 125°C − 0.888W × 50 ^°C _W
T_A(MAX) = 81°C
Using an external LDO to supply VDD (as in Figure 5)
can lower power dissipation in the controller and reduce
junction temperature by supplying VDD externally. Using
an external regulator, the power dissipated in the
controller is reduced to:
P_DISS = (5V × (37nC × 4) × 500kHz = 0.37W
Careful selection and temperature rise calculations of
the external LDO should be done to prevent an
excessively high LDO junction temperature.
MIC2155/2156
UVLO
Separate UVLO circuits monitor VIN1, VIN2 and VDD.
Switching on Channel 1 is inhibited until the voltage on
the VIN1 and VDD pins is greater than their respective
UVLO thresholds. The gate drive on Channel 2 is
inhibited until the VIN2 pin voltage exceeds its UVLO
threshold.
Individual UVLO thresholds are necessary to allow
proper operation from separate input supplies. The VIN1
threshold prevents the IC from switching if the input
voltage is too low to properly source the VDD voltage.
The VIN2 UVLO threshold is lower than VIN1 to allow
operation from a low voltage input.
Channel 1 will switch and provide a regulated output
voltage even if the VIN2 UVLO prevents Channel 2 from
switching.
Power Good
The power good signal asserts high when the output
voltage is greater than the power good threshold. The
power good circuit compares a portion of the reference
voltage to the voltage on the feedback pin. The output is
an open drain FET as shown in Figure 7. To assert high
it must be pulled up to A_VDD through a resistor.
AV_DD
PG Comparator
FB1
PGOOD
BandGap-10%
Figure 7. Power Good
The power good signal may be connected to the enable
pin of other power supplies and used to sequence the
other outputs.
Oscillator and Frequency Synchronization
The internal oscillator free runs at a fixed frequency and
requires no external components. The oscillator
generates two clock signals that are 180° out of phase
with each other. This forces each channel of the
controller to switch 180° out of phase, which reduces
input and output ripple current.
The internal oscillator generates a clock signal and ramp
signal. The clock signal terminates the switching cycle
for each channel. The ramp voltage for Channel 1 is
compared with the output of the error amplifier and
regulates the output voltage. The ramp signal for
Channel 2 is compared with the Channel 2 error
amplifier output and forces the output current of Channel
2 to match Channel 1.
May 2009
14
M9999-052709-A
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