MIC2342 Datasheet, PDF (23/32 Pages) Micrel Semiconductor – Dual-Slot PCI Express® Hot-Plug Controller

Micrel, Inc.
MIC2342/2342R
Figure 7. MIC2342R Auto-Retry Timing Diagram and Operation in Current-limit
Thermal Shutdown
The internal VAUX[A/B] MOSFETs are protected against
damage not only by current limiting, but by
overtemperature protection as well. Should an
overcurrent condition on either VAUX[A] or VAUX[B]
raise the junction temperature of the MIC2342 to 140°C,
all of the outputs for that corresponding slot (including
VAUX) will be shut off and that slot’s /FAULT_AUX
output will be asserted. The slot’s /FAULT_MAIN output
will not be asserted. The other slot’s operating condition
will remain unaffected. However, should the MIC2342’s
die temperature exceed 160°C because of an
overcurrent fault condition on both VAUX[A] and
VAUX[B], both slots (all outputs, including VAUXA and
VAUXB) will be shut off. In this case, both
/FAULT_AUX[A/B] output signals will be asserted; the
/FAULT_MAIN[A/B] output signals will not be asserted.
Plug-in Card Retention Switch Inputs
Two pins on the MIC2342 are available for use as card
retention switch inputs, /CRSW[A/B]. These pins are
internally pulled-up by 45kΩ resistors to VSTBY and
prevent the enabling of all gate drive circuits on
12GATE[A/B], 3VGATE[A/B], and VAUX[A/B] unless
these input pins are asserted LOW. In addition, each of
these inputs exhibits an internal debounce delay time of
approximately 10ms.
/FORCE_ON[A/B] Inputs
These level sensitive, asserted active-low digital inputs
are internally pulled up to VSTBY through a weak
current source and are intended for diagnostics during
the debug phase of the system design involving the
MIC2342. In asserting /FORCE_ON[A/B] LOW, all three
of the respective slot’s outputs (+12V, +3.3V, and VAUX)
will turn on. However, all protections for those outputs
are disabled. This explicitly includes all overcurrent and
short circuit protections, and on-chip thermal protection
for the VAUX supplies. Additionally, asserting a slot’s
/FORCE_ON[A/B] input will disable all of its input and
output UVLO protections, with the sole exception of that
asserting either or both of the /FORCE_ON[A/B] inputs
will not disable the VSTBY[A/B] input UVLO.
Asserting /FORCE_ON[A/B] LOW will cause the
respective slot’s /PWRGD[A/B], and /DLY_PWRGD[A/B]
output signals to be asserted LOW while the
/FAULT_MAIN[A/B], the /FAULT_AUX[A/B}, the /INT,
and the SYSPWRGD output signals to enter their open-
drain state.
June 2008
23
M9999-062008-B