MIC2358YLQ Datasheet, PDF (22/29 Pages) Micrel Semiconductor – IEEE 802.3af Octal Power Sourcing Equipment Controller

Micrel, Inc.
Port Event Register
SMBus Address: 0x07, 0x0F, 0x17, 0x1F, 0x27, 0x2F, 0x37, 0x3F
Read Only, Clear on Read
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
–
power_ valid_
invalid_
short_circuit
denied
signature signature
overload
Bit 1
dc_mps_absent
MIC2358YLQ
Bit 0
ac_mps_absent
Name
Description
power_denied
Set when the port was not powered, or power was removed, and the state machine enters
the power_denied state.
valid_signature
Set when a valid signature is detected.
Invalid_signature
Set when an invalid signature is detected.
short_circuit
Set when a short circuit condition occurs.
overload
Set when an overload condition occurs.
dc_mps_absent
Set when the DC maintain power signature drops out.
ac_mps_absent
Set when the AC maintain power signature drops out.
Notes:
1. Port EVENT register bits correspond to PSE Status register bit[12..7] from Table 33-16 of IEEE Std 802.3af-2005. MPS Absent bit is reported
separately as dc_mps_absent and ac_mps_absent.
2. Port EVENT register is associated with other behaviors of the MIC2358YLQ. The first behavior is the assertion of the /SMBINT pin (pin 58). If the
port has an event occur that is not masked by the global EVENT_MASK register, then the /SMBINT pin will be asserted, letting the host know that
an event has occurred.
3. The second behavior is the event holding. If the event hold bit in the port OPTION register is clear and an unmasked event occurs on this port,
then the MIC2358YLQ will attempt another at detection on this port. If the event_hold bit in the port OPTION register is set and an unmasked
event occurs on this port, then the MIC2358YLQ will make no further attempts to do detection on this port until the host has cleared the
event_hold bit. This gives the host the opportunity to analyze what caused the event on the port and deal with it accordingly, prior to trying to
power up the port again.
Global Configuration Register
SMBus Address: 0x40
Read and Write
Bit 7 Bit 6
Bit 5
–
–
–
Bit 4
_
Bit 3
enable_spm
Bit 2
Ignore_class_
overlaod
Bit 1
alternative_b
Bit 0
restore_default
_setup
Name
enable_spm
ignore_class_overload
Default
1
Note 1
alternative_b
Note 2
restore_default_setup
0
Notes:
1. Initial state determined by ICO input pin.
2. Initial state determined by ALTB input pin.
Description
Turns on the shared power management feature.
Inhibits shutdown of port power if its current exceeds the class-dependent
overload current, i.e. overload current will be equal to Class 0 level. Shutdown
will still occur if the current exceeds the short-circuit threshold.
Enables Alternative B behavior, which adds a backoff delay following an
invalid detection.
Software Reset. Forces the controller to restart and return all settings to
default values. This bit will be cleared once the reset is complete.
July 2010
22
M9999-070810