PL500-15 Datasheet, PDF (2/5 Pages) Micrel Semiconductor – Low Phase Noise VCXO (1MHz to 18MHz)

DIE PAD LAYOUT
32 mil
PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
(812,986)
DIE SPECIFICATIONS
1 XIN
8
XOUT
OE^ 7
2 VCON
VDD 6
3 DIVSEL^
CLK 5
4 GND
DIE ID: PL500-15: C500A-1111-12
PL500-16: C500A-1111-11
Y (0,0)
X _{Note: ^ denotes internal pull up}
Name
Size
Reverse side
Pad dimensions
Thickness
Value
39 x 32 mil
GND
80 micron x 80 micron
8 mil
DIE PAD ASSIGNMENT
Name
Pin#
SOP-8 SOT23-6
XIN
1
3
VCON
2
1
DIVSEL 3
-
GND
4
2
CLK
5
6
VDD
6
5
OE
7
-
XOUT
8
4
Die Pad Position
X (m) Y (m)
94.183 768.599
94.157 605.029
94.183 331.756
94.193
715.472
715.307
140.379
203.866
455.726
715.472 626.716
476.906 888.881
Type
I
P
I
P
O
P
I
I
Description
Crystal input pin.
Frequency Control Voltage input pin.
Divider Selection input pin. Default Logic 1 for
SOT23 package. See Divider Selection Logic
Levels table on Page 1.
Ground pin.
Output clock pin.
VDD power supply pin.
Output Enable input pin. Disables the output
when low. Internal pull-up enables output by
default if pin is not connected to low. Default
“Enabled” (Logic 1) for SOT23 package.
Crystal output pin.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 7/01/10 Page 2